EM639165_07 Datasheet, PDF (46/73 Pages) Etron Technology, Inc. – 8Mega x 16 Synchronous DRAM (SDRAM)

EtronTech
EM639165
Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency=2)
CLK
CKE
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CS#
RAS#
CAS#
WE #
BA0,1
A10
RAx
A0~A9,A11
RAx
CAx
CAy
DQM
DQ ^Hi-Z
Ax0 Ax1 Ax2 Ax3
DAy0 DAy1
DAy3
Activate
Read
Command Command
Bank A
Bank A
Write The Write Data
Command is Masked with a
Bank A Zero Clock
Latency
CAz
Az0 Az1
Az3
Read
Command
Bank A
The Read Data
is Masked with a
Two Clock
Latency
46
Rev 1.6 Feb. 2007