EM6AB080TSB-4G Datasheet, PDF (53/62 Pages) Etron Technology, Inc. – 64M x 8 bit DDR Synchronous DRAM (SDRAM

EtronTech
Figure 35. Self Refresh Mode
CK
CK
CKE
COMMAND
t_CK
t_CH
t_CL
t_IS t_IH
t_IS t_IH
NOP
t_IS
AR
ADDR
EM6AB080
Clock must be stable before
Exiting Self Refresh mode
t_IS
NOP
VALID
t_IS t_IH
VALID
DQS
DQ
DM
t_RP*
Enter Self Refresh
mode
t_XSNR/
t_XSRD**
Exit Self Refresh
mode
* = Device must be in the All banks idle state prior to entering Self Refresh mode
** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CK) is
required before a READ command can be applied.
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Etron Confidential
53
Rev.1.1 Dec. /2013