SEN01G64D1BF1SA-25R Datasheet, PDF (9/14 Pages) List of Unclassifed Manufacturers – 1GB DDR2 – SDRAM SO-DIMM

Data Sheet
Rev.1.2 12.12.2010
DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
AC CHARACTERISTICS
PARAMETER
Clock cycle time CL = 6
CL = 5
CL = 4
CL = 3
CK high-level width
CK low-level width
Half clock period
SYMBOL
t_CK (6)
t_CK (5)
t_CK (4)
t_CK (3)
t_CH
t_CL
t_HP
Access window (output) of DQS t_AC
from CK/CK#
Data-out high-impedance
t_HZ
window from CK/CK#
Data-out low-impedance window t_LZ
from CK/CK#
DQ and DM input setup time
relative to DQS
t_DS(base)
5300-555
MIN MAX
-
-
3.0
8.0
3.75
8.0
5.0
8.0
0.48 0.52
0.48 0.52
min
(tCH, tCL)
-0.45 +0.45
-0.45
(= tAC min)
+0.45
(= tAC max)
+0.45
(= tAC max)
0.10
6400-666
MIN MAX
2.5
8.0
3.0
8.0
3.75
8.0
-
-
0.48 0.52
0.48 0.52
min
(tCH, tCL)
-0.40 +0.40
-0.40
(= tAC min)
+0.40
(= tAC max)
+0.40
(= tAC max)
0.05
Unit
ns
ns
ns
ns
tCK
tCK
ps
ns
ns
ns
ns
DQ and DM input hold time
relative to DQS
t_DH(base)
0.30
0.125
ns
DQ and DM input pulse width
( for each input )
t_DIPW
0.35
0.35
tCK
Data hold skew factor
t_QHS
0.34
0.3 ns
DQ-DQS hold, DQS to first DQ t_QH
to go non-valid, per access
tHP - tQHS
tHP - tQHS
ns
Data valid output window
t_DVW
tQH -
tDQSQ
tQH -
tDQSQ
ns
DQS input high pulse width
DQS input low pulse width
DQS output access time from
CK/CK#
t_DQSH
t_DQSL
t_DQSCK
0.35
0.35
-0.40
+0.40
0.35
0.35
-0.35
tCK
tCK
+0.35 ns
DQS falling edge to CK rising t_DSS
- setup time
0.2
0.2
tCK
DQS falling edge from CK rising t_DSH
- hold time
0.2
0.2
tCK
DQS –DQ skew, DQS to last
t_DQSQ
DQ valid, per group, per access
0.24
0.2 ns
DQS read preamble
DQS read postamble
DQS write preamble
t_RPRE
t_RPST
t_WPRE
0.9
1.1
0.9
1.1 tCK
0.4
0.6
0.4
0.6 tCK
0.35
0.35
tCK
DQS write preamble setup time t_WPRES
0
0
ns
DQS write postamble
t_WPST
0.4
0.6
0.4
0.6 tCK
Positive DQS latching edge to
associated clock edge
t_DQSS
- 0.25 + 0.25 - 0.25 + 0.25 tCK
Write command to first DQS
latching transition
WL-
tDQSS
WL+
tDQSS
WL-
tDQSS
WL+
tDQSS
tCK
Address and control input pulse t_IPW
width ( for each input )
0.6
0.6
tCK
Swissbit AG
Industriestrasse 4
Ch-9552 Bronschhofen
Fon: [phone]
Fax: [phone]
www.swissbit.com
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