RHFAC245D03V Datasheet, PDF (9/25 Pages) List of Unclassifed Manufacturers – STANDARD MICROCIRCUIT DRAWING

TABLE IA. Electrical performance characteristics - Continued.
3/ RHA parts for device type 02 of this drawing have been characterized through all levels M, D, P, L, R, and F of irradiation.
However, these devices are only tested at the 'F' level. Pre and post irradiation values are identical unless otherwise
specified in table IA. When performing post irradiation electrical measurements for any RHA level, TA = +25°C.
4/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and
the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum
and maximum limits, as applicable, listed herein. All devices shall meet or exceed the limits specified in table IA, as
applicable, at 3.0 V ≤ VCC ≤ 3.6 V and 4.5 V ≤ VCC ≤ 5.5 V.
5/ The VOH and VOL tests shall be tested at VCC = 3.0 V and 4.5 V. The VOH and VOL tests are guaranteed, if not tested, for
other values of VCC. Limits shown apply to operation at VCC = 3.3 V ±0.3 V and VCC = 5.0 V ±0.5 V. Tests with input
current at +50 mA or -50 mA are performed on only one input at a time with duration not to exceed 10 ms. Transmission
driving tests may be performed using VIN = VCC or GND. When VIN = VCC or GND is used, the test is guaranteed for
VIN = VIH minimum and VIL maximum.
6/ The VIH and VIL tests are not required if applied as forcing functions for VOH and VOL tests.
7/ The maximum limit for this parameter at 100 krads (Si) is 4 µA.
8/ Power dissipation capacitance (CPD) determines both the power consumption (PD) and dynamic current consumption (IS).
Where:
PD = (CPD + CL) (VCC x VCC)f + (ICC x VCC)
IS = (CPD + CL) VCCf + ICC
For both PD and IS, f is the frequency of the input signal and CL is the external output load capacitance.
9/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic
patterns used for fault detection. The test vectors used to verify the truth table shall, at a minimum, test all functions of
each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth
table in figure 3 herein. Functional tests shall be performed in sequence as approved by the qualifying activity on qualified
devices. Allowable tolerances in accordance with MIL-STD-883 for the input voltage levels may be incorporated. For
output measurements, H ≥ 0.7VCC, L ≤ 0.3VCC.
10/ AC limits at VCC = 5.5 V are equal to the limits at VCC = 4.5 V and guaranteed by testing at VCC = 4.5 V. AC limits at
VCC = 3.6 V are equal to the limits at VCC = 3.0 V and guaranteed by testing at VCC = 3.0 V. Minimum ac limits for
VCC = 5.5 V are 1.0 ns and guaranteed by guardbanding the VCC = 4.5 V minimum limits to 1.5 ns. For propagation delay
tests, all paths must be tested.
TABLE IB. SEP test limits. 1/ 2/
Device
type
02
SEP
No SEL
TC =
temperature
±10°C
+125°C
VCC
Bias VCC = 5.5 V
Effective LET
≤ 93 MeV-cm²/mg
1/ For SEP test conditions, see 4.4.4.2 herein.
2/ Technology characterization and model verification supplemented by in-line data may be used in
lieu of end-of-line testing. Test plan must be approved by TRB and qualifying activity.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
H
5962-87758
SHEET
9