N78E517A Datasheet, PDF (87/141 Pages) List of Unclassifed Manufacturers – Microcontroller

XICON – External Interrupt Control (bit-addressable)
7
6
5
4
PX3^[1]
EX3
IE3
IT3
r/w
r/w
r/w
r/w
Address: C0H
3
PX2^[1]
r/w
2
1
0
EX2
IE2
IT2
r/w
r/w
r/w
reset value: 0000 0000b
Bit
Name
Description
7
PX3 External interrupt 3 priority low bit.
6
EX3 Enable external interrupt 3.
0 = Disable external interrupt 3.
1 = Enable interrupt generated by INT3 pin (P4.2).
5
IE3
External interrupt 3 edge flag.
This flag is set via hardware when an edge/level of type defined by IT3 is detect-
ed. If IT3 = 1, this bit will remain set until cleared via software or at the beginning
of the External Interrupt 3 service routine. If IT3 = 0, this flag is the inverse of the
INT3 input signal‟s logic level.
4
IT3
External interrupt 3 type select.
This bit selects whether the INT3 pin will detect falling edge or low level triggered
interrupts.
0 = INT3 is low level triggered.
1 = INT3 is falling edge triggered.
3
PX2 External interrupt 2 priority low bit.
2
EX2 Enable external interrupt 2.
0 = Disable external interrupt 2.
1 = Enable interrupt generated by INT2 pin (P4.3).
1
IE2
External interrupt 2 edge flag.
This flag is set via hardware when an edge/level of type defined by IT2 is detect-
ed. If IT2 = 1, this bit will remain set until cleared via software or at the beginning
of the External Interrupt 2 service routine. If IT2 = 0, this flag is the inverse of the
INT2 input signal‟s logic level.
0
IT2
External interrupt 2 type select.
This bit selects whether the INT2 pin will detect falling edge or low level triggered
interrupts.
0 = INT2 is low level triggered.
1 = INT2 is falling edge triggered.
[1] PX2 and PX3 are used in combination with the PX2H (IPH.6) and PX3H (IPH.7) respectively to determine the priority of
external interrupt 2 and 3. See Table 17–2. Interrupt Priority Level Setting for correct interrupt priority configuration.
The External Interrupts INT0 and INT1 can be either edge or level triggered depending on bits IT0 (TCON.0)
and IT1 (TCON.2). The bits IE0 (TCON.1) and IE1 (TCON.3) are the flags which are checked to generate the
interrupt. In the edge triggered mode, the INT0 or INT1 inputs are sampled in every machine-cycle. If the
sample is high in one cycle and low in the next, then a high to low transition is detected and the interrupts re-
quest flag IE0 or IE1 will be set. Since the external interrupts are sampled every machine-cycle, they have to
be held high or low for at least one complete machine-cycle. The IE0 and IE1 are automatically cleared when
the interrupt service routine is called. If the level triggered mode is selected, then the requesting source has to
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Publication Release Date: September 4, 2012
Revision: V2.2