N78E517A Datasheet, PDF (86/141 Pages) List of Unclassifed Manufacturers – Microcontroller

N78E517A Data Sheet
EIPH – Extensive Interrupt Priority High^[1]
7
6
5
4
-
-
-
-
-
-
-
-
Address: BBH
3
2
1
0
-
PBODH
PPDTH
PSPIH
-
r/w
r/w
r/w
reset value: 0000 0000b
Bit
Name
Description
7:3
-
Reserved.
2
PBODH Brown-out detection interrupt priority high bit.
1
PPDTH Power Down waking-up timer interrupt priority high bit.
0
PSPIH SPI interrupt priority high bit.
[1] EIPH is used in combination with the EIP to determine the priority of each interrupt source. See Table 17–2. Interrupt
Priority Level Setting for correct interrupt priority configuration.
TCON – Timer 0 and 1 Control (bit-addressable)
7
6
5
4
3
TF1
TR1
TF0
TR0
IE1
r/w
r/w
r/w
r/w
r/w
Address: 88H
2
1
0
IT1
IE0
IT0
r/w
r/w
r/w
reset value: 0000 0000b
Bit
Name
Description
3
IE1
External interrupt 1 edge flag.
This flag is set via hardware when an edge/level of type defined by IT1 is detect-
ed. If IT1 = 1, this bit will remain set until cleared via software or at the beginning
of the External Interrupt 1 service routine. If IT1 = 0, this flag is the inverse of the
INT1 input signal‟s logic level.
2
IT1
External interrupt 1 type select.
This bit selects whether the INT1 pin will detect falling edge or low level triggered
interrupts.
0 = INT1 is low level triggered.
1 = INT1 is falling edge triggered.
1
IE0
External interrupt 0 edge flag.
This flag is set via hardware when an edge/level of type defined by IT0 is detect-
ed. If IT0 = 1, this bit will remain set until cleared via software or at the beginning
of the External Interrupt 0 service routine. If IT0 = 0, this flag is the inverse of the
INT0 input signal‟s logic level.
0
IT0
External interrupt 0 type select.
This bit selects whether the INT0 pin will detect falling edge or low level triggered
interrupts.
0 = INT0 is low level triggered.
1 = INT0 is falling edge triggered.
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