N78E517A Datasheet, PDF (53/141 Pages) List of Unclassifed Manufacturers – Microcontroller

13. SERIAL PORT
N78E517A includes one enhanced full duplex serial port. The serial port supports three modes of full duplex
UART (Universal Asynchronous Receiver and Transmitter) in Mode 1, 2, and 3. Full duplex means it can
transmit and receive simultaneously. The serial port is also receive-buffered, meaning it can commence recep-
tion of a second byte before a previously received byte has been read from the register. The serial port receive
and transmit registers are both accessed at SBUF. Writing to SBUF loads the transmit register, and reading
SBUF accesses a physically separate receive register. There are four operation modes in serial port. In all four
modes, transmission initiates by any instruction that uses SBUF as a destination register. Note that before se-
rial port function works, the port latch bits of P3.0 and P3.1 (for RXT and TXD pins) have to be set to 1.
SCON – Serial Port Control (bit-addressable)
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Address: 98H
reset value: 0000 0000b
Bit
Name
Description
7
SM0 Serial port mode select.
See Table 13–1. Serial Port Mode Description for details.
6
SM1
5
SM2 Multiprocessor communication mode enable.
The function of this bit is dependent on the serial port mode.
Mode 0:
This bit has no effect.
Mode 1:
This bit checks valid stop bit.
0 = Reception is always valid no matter the logic level of stop bit.
1 = Reception is ignored if the received stop bit is not logic 1.
Mode 2 or 3:
For multiprocessor communication.
0 = Reception is always valid no matter the logic level of the 9^th bit.
1 = Reception is ignored if the received 9^th bit is not logic 1.
4
REN Receive enable.
0 = Disable serial port reception.
1 = Enable serial port reception in Mode 1,2, and 3. In Mode 0, reception is initial-
ized by the condition REN = 1 and RI = 0.
3
TB8
9^th transmit bit.
This bit defines the state of the 9^th transmission bit in serial port Mode 2 and 3. It
is not used in Mode0 and 1.
2
RB8
9^th receive bit.
The bit identifies the logic level of the 9^th received bit in Modes 2 and 3. In Mode
1, if SM2 0, RB8 is the logic level of the received stop bit. RB8 is not used in
Mode 0.
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Publication Release Date: September 4, 2012
Revision: V2.2