AT25SF081 Datasheet, PDF (8/47 Pages) List of Unclassifed Manufacturers – 8-Mbit, 2.5V Minimum SPI Serial Flash Memory with Dual-I/O and Quad-IO Support

Table 5-1. Command Listing
Command
Deep Power-Down
Resume from Deep Power-Down
Resume from Deep Power-Down and
Read ID
Opcode
B9h
1011 1001
ABh
1010 1011
Clock
Frequency
Address Dummy
Bytes Bytes
Up to 104 MHz
0
0
Up to 104 MHz
0
0
Data
Bytes
0
0
Section
Link
11.3
11.4
ABh
1010 1011 Up to 104 MHz
0
3
1
11.4
6. Read Commands
6.1 Read Array (0Bh and 03h)
The Read Array command can be used to sequentially read a continuous stream of data from the device by simply
providing the clock signal once the initial starting address is specified. The device incorporates an internal address
counter that automatically increments every clock cycle.
Two opcodes (0Bh and 03h) can be used for the Read Array command. The use of each opcode depends on the
maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at any clock
frequency up to the maximum specified by f_CLK, and the 03h opcode can be used for lower frequency read operations up
to the maximum specified by f_RDLF.
To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (0Bh or 03h) must be
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
starting address location of the first byte to read within the memory array. Following the three address bytes, an
additional dummy byte needs to be clocked into the device if the 0Bh opcode is used for the Read Array operation.
After the three address bytes (and the dummy byte if using opcode 0Bh) have been clocked in, additional clock cycles
will result in data being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte
(0FFFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array
(000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into high-impedance state. The CS pin can
be deasserted at any time and does not require a full byte of data be read.
Figure 6-1. Read Array - 03h Opcode
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AT25SF081
8
DS-25SF081A–045B–5/2014