AT25SF081 Datasheet, PDF (3/47 Pages) List of Unclassifed Manufacturers – 8-Mbit, 2.5V Minimum SPI Serial Flash Memory with Dual-I/O and Quad-IO Support

Table 1-1. Pin Descriptions (Continued)
Symbol Name and Function
Asserted
State
Type
SO (I/O₁)
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin
is always clocked out on the falling edge of SCK.
With the Dual-Output Read commands, the SO Pin remains an output pin (I/O₀) in
conjunction with other pins to allow two bits of data on (I/O_1-0) to be clocked in on every
falling edge of SCK
To maintain consistency with the SPI nomenclature, the SO (I/O₁) pin will be referenced as
the SO pin unless specifically addressing the Dual-I/O modes in which case it will be
referenced as I/O₁
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
-
Input/Output
WP
(I/O₂)
HOLD
(I/O₃)
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please
refer to “Program/Erase Suspend (75h)” on page 17 for more details on protection features
and the WP pin.
With the Quad-Input Byte/Page Program command, the WP pin becomes an input pin (I/O₂)
and, along with other pins, allows four bits (on I/O_3-0) of data to be clocked in on every rising
edge of SCK. With the Quad-Output Read commands, the WP Pin becomes an output pin
(I/O₂) in conjunction with other pins to allow four bits of data on (I/O3_3-0) to be clocked in on
every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the WP (I/O₂) pin will be referenced as
the WP pin unless specifically addressing the Quad-I/O modes in which case it will be
referenced as I/O₂
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected
to V_CC whenever possible.
HOLD: The HOLD pin is used to temporarily pause serial communication without
deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK
pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an
effect on internally self-timed operations such as a program or erase cycle. Please refer to
“Hold Function” on page 31 for additional details on the Hold operation.
With the Quad-Input Byte/Page Program command, the HOLD pin becomes an input pin
(I/O₃) and, along with other pins, allows four bits (on I/O_3-0) of data to be clocked in on every
rising edge of SCK. With the Quad-Output Read commands, the HOLD Pin becomes an
output pin (I/O₃) in conjunction with other pins to allow four bits of data on (I/O3_3-0) to be
clocked in on every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the HOLD (I/O₃) pin will be referenced
as the HOLD pin unless specifically addressing the Quad-I/O modes in which case it will be
referenced as I/O₃
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be
used. However, it is recommended that the HOLD pin also be externally connected to V_CC
whenever possible.
-
Input/Output
-
Input/Output
DEVICE POWER SUPPLY: The V_CC pin is used to supply the source voltage to the device.
V_CC
Operations at invalid V_CC voltages may produce spurious results and should not be
-
attempted.
Power
GND
GROUND: The ground reference for the power supply. GND should be connected to the
system ground.
-
Power
AT25SF081
3
DS-25SF081A–045B–5/2014