AT25SF081 Datasheet, PDF (4/47 Pages) List of Unclassifed Manufacturers – 8-Mbit, 2.5V Minimum SPI Serial Flash Memory with Dual-I/O and Quad-IO Support

Figure 1-1. 8-SOIC, 8-TSSOP (Top View)
CS 1
SO 2
WP 3
GND 4
8 VCC
7 HOLD
6 SCK
5 SI
2. Block Diagram
Figure 2-1. Block Diagram
Figure 1-2. 8-UDFN (Top View)
CS 1
SO 2
WP 3
GND 4
8 VCC
7 HOLD
6 SCK
5 SI
Control and
CS
Protection Logic
SCK
SI (I/O0)
SO (I/O1)
Interface
Control
And
Logic
Y-Decoder
WP (I/O2)
HOLD (I/O3)
X-Decoder
Note: I/O3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands.
I/O Buffers
and Latches
SRAM
Data Buffer
Y-Gating
Flash
Memory
Array
3. Memory Array
To provide the greatest flexibility, the memory array of the AT25SF081 can be erased in four levels of granularity
including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing
both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the
breakdown of each erase level.
AT25SF081
4
DS-25SF081A–045B–5/2014