N78E059A Datasheet, PDF (69/138 Pages) List of Unclassifed Manufacturers – Microcontroller

Bit
Name
Description
1
SPR1 SPI clock rate select.
These two bits select four grades of SPI clock divider.
0
SPR0
SPR1 SPR0 Divider SPI clock rate
0
0
16 1.25M bit/s
0
1
32
625k bit/s
1
0
64
312k bit/s
1
1
128
156k bit/s
The clock rates above are illustrated under FPERIPH = 20MHz condition.
Table 14–1. Slave Select Pin Configurations
DISMODF
0
1
1
SSOE
x
0
1
Master Mode (MSTR = 1) Slave Mode (MSTR = 0)
SS input for Mode Fault
General purpose I/O
SS Input for Slave select
Automatic SS output
SPSR – Serial Peripheral Status Register
7
6
5
4
3
2
SPIF
WCOL
SPIOVF
MODF DISMODF
-
r/w
r/w
r/w
r/w
r/w
-
Address: F4H
1
0
-
-
-
-
reset value: 0000 0000b
Bit
Name
Description
7
SPIF SPI complete flag.
This bit is set to logic 1 via hardware while an SPI data transfer is complete or an
receiving data has been moved into the SPI read buffer. If ESPI (EIE .0) and EA
are enabled, an SPI interrupt will be required. This bit must be cleared via soft-
ware. Attempting to write to SPDR is inhibited if SPIF is set.
6
WCOL Write collision error flag.
This bit indicates a write collision event. Once a write collision event occurs, this
bit will be set. It must be cleared via software.
5
SPIOVF SPI overrun error flag.
This bit indicates an overrun event. Once an overrun event occurs, this bit will be
set. If ESPI and EA are enabled, an SPI interrupt will be required. This bit must
be cleared via software.
4
MODF Mode Fault error flag.
This bit indicates a Mode Fault error event. If SS pin is configured as Mode
Fault input (MSTR = 1 and DISMODF = 0) and SS is pulled low by external de-
vices, a Mode Fault error occurs. Instantly MODF will be set as logic 1. If ESPI
and EA are enabled, an SPI interrupt will be required. This bit must be cleared
via software.
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Publication Release Date: March 11, 2010
Revision: V2.0