N78E059A Datasheet, PDF (14/138 Pages) List of Unclassifed Manufacturers – Microcontroller

N78E059A/N78E055A Data Sheet
5. MEMORY ORGANIZATION
A standard 8051 based MCU divides the memory into two different sections, the Program Memory and the Da-
ta Memory. The Program Memory is used to store the instruction codes, whereas the Data Memory is used to
store data or variations during the program execution.
Data Memory occupies a separate address space from Program Memory. In N78E059A/N78E055A, there are
256 bytes of internal scratch-pad RAM and up to 64k bytes of memory space for external Data Memory. The
MCU generates the 16-bit or 8-bit addresses, read and write strobe signals ( RD and WR , respectively) during
external Data Memory access. For many applications which need more internal RAM, N78E059A/N78E055A
possesses on-chip 1k bytes of RAM (called XRAM) accessed by MOVX instruction.
The whole embedded flash is divided into 4 banks, APROM for storage of user‟s program code, Data Flash for
parameter data storage, LDROM for ISP program and CONFIG bytes. Each bank is accumulated page by
page and the page size is 256 bytes. The flash control unit supports Page Erase, Byte Program, and Byte
Read modes. The external writer tools though specific I/O pins and the internal ISP (In System Programming)
function both can perform these modes.
5.1 Internal Program Memory
Program Memory is the one, which stores the program codes to execute, as shown in Figure 5–1. While EA
pin is pulled high and after any reset, the CPU begins execution from location 0000H where should be the
starting point of the user‟s application code. To service the interrupts, the interrupt service locations (called in-
terrupt vectors) should be located in the Program Memory. Each interrupt is assigned with a fixed location in
the Program Memory. The interrupt causes the CPU to jump to that location with where it commences execu-
tion of the interrupt service routine (ISR). External Interrupt 0, for example, is assigned to location 0003H. If
External Interrupt 0 is going to be used, its service routine must begin at location 0003H. If the interrupt is not
going to be used, its service location is available as general purpose Program Memory.
The interrupt service locations are spaced at an interval of 8 bytes: 0003H for External Interrupt 0, 000BH for
Timer 0, 0013H for External Interrupt 1, 001BH for Timer 1, etc. If an interrupt service routine is short enough
(as is often the case in control applications), it can reside entirely within that 8-byte interval. However longer
service routines should use a JMP instruction to skip over subsequent interrupt locations if other interrupts are
in use.
N78E059A/N78E055A provides two internal Program Memory bank APROM and LDROM. Although they both
behave the same as the standard 8051 Program Memory, they play different rules according to their ROM
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Publication Release Date: March 11, 2010
Revision: V2.0