C8051F36X Datasheet, PDF (6/13 Pages) List of Unclassifed Manufacturers – C8051F36x DEVELOPMENT KIT

C8051F36x-DK
5. Target Board
The C8051F36x Development Kit includes a target board with a C8051F360 device pre-installed for evaluation and
preliminary software development. Numerous input/output (I/O) connections are provided to facilitate prototyping
using the target board. Refer to Figure 3 for the locations of the various I/O connectors.
P1 96-pin female connector
P2 Power connector (Accepts input from 7 to 15 VDC unregulated power adapter.)
P3 Analog I/O terminal block
P4 USB connector (for CP2102 USB-to-UART bridge)
J1
Power supply header (Selects power from the USB Debug Adapter, P1 Power Adapter, or USB
power if P4 is connected. Only one power option should be selected at one time.)
J2 Port 0 header
J3 Port 1 header
J4 Port 2 header
J5
Port 3 header
J6
Port 4 header
J7
Connects the +3 V supply net to the VDD supply net
J8
Supply signal header
J9 Debug connector for debug adapter interface
J10, J11External crystal port pin enable connectors
J12 Port I/O jumper configuration block
J13 Jumper connection for potentiometer to pin 2.5
J14 Jumper connection for potentiometer source to +3 V
J15 Jumper connection for pin 0.3 to capacitors (used when VREF is internally generated)
J16 Jumper connection for pin 0.4 to resistor/capacitor (used to convert IDAC output to a voltage)
J18 Connects the +3 V supply net to the AV+ supply net
SA-TB52PCB
P1
R10
PORT_4
P3.0 P3.1 RESET
P3.2
D4
P3.3
USB
ACTIVE
J14
J13
J12
D3
D5
P3.0
SW3.0
P3.1
SW3.1
J6
P3.2
P3.2_LED U3
P4
PORT_3
P3.3
P0.1
P3.3_LED
TX
P0.2
RX
SILICON LABS ^P3.4
RTS
www.silabs.com
P3.5
CTS
POWER
P2
J5
C8051F360 TB
J1
GND
GND
PORT_2
AV+
VDD
F360
+3VD
VBUS
J8
J4
PORT_1
J15
U1
P0.3
VREF
P0.4
IDAC
J16 ^PORT_0
DEBUG
J11
J10
J9
J3
J2
P3
D2
PWR
Figure 3. C8051F360 Target Board
6
Rev. 0.3