LM3S611 Datasheet, PDF (55/409 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S611 Data Sheet
5.4.1.8
5.4.2
BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO
ports. The BYPASS Data Register is a single-bit shift register. This instruction improves test
efficiency by allowing components that are not needed for a specific test to be bypassed in the
JTAG scan chain by loading them with the BYPASS instruction. Please see “BYPASS Data
Register” on page 55 for more information.
Data Registers
The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary
Scan, APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is
discussed in the following sections.
5.4.2.1
IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-3. The standard requires that every JTAG-compliant device implement either the
IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This allows auto configuration test tools to determine which instruction is the default
instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly, and
program development and debug. To facilitate the use of auto-configuration debug tools, the
IDCODE instruction outputs a value of 0x1BA00477. This value indicates an ARM Cortex-M3,
Version 1 processor. This allows the debuggers to automatically configure themselves to work
correctly with the Cortex-M3 during debug.
Figure 5-3. IDCODE Register Format
31
28 27
TDI
Version
Part Number
12 11
Manufacturer ID
10
1 ^TDO
5.4.2.2
BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-4. The standard requires that every JTAG-compliant device implement either the
BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This allows auto configuration test tools to determine which instruction is the default
instruction.
Figure 5-4. BYPASS Register Format
TDI
0
0 ^TDO
5.4.2.3
Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 5-5. Each GPIO pin, in a
counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data
Register. Each GPIO pin has three associated digital signals that are included in the chain. These
April 27, 2007
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Preliminary