LM3S611 Datasheet, PDF (102/409 Pages) List of Unclassifed Manufacturers – Microcontroller

Internal Memory
7.2.2.4
7.3
7.3.1
If the user will also be using the FMPRE bits to protect flash memory from being read as data (to
mark sets of 2 KB blocks of flash memory as execute-only), these one-time-programmable bits
should be written at the same time that the debug disable bits are programmed. Mechanisms to
execute the one-time code sequence to disable all debug access include:
„ Selecting the debug disable option in the Stellaris boot loader
„ Loading the debug disable sequence into SRAM and running it once from SRAM after
programming the final end application code into flash
Flash Memory Programming
Writing the flash memory requires that the code be executed out of SRAM to avoid corrupting or
interrupting the bus timing. Flash pages can be erased on a page basis (1 KB in size), or by
performing a mass erase of the entire flash.
All erase and program operations are performed using the Flash Memory Address (FMA), Flash
Memory Data (FMD) and Flash Memory Control (FMC) registers. See section 7.3 for examples.
Initialization and Configuration
This section shows examples for using the flash controller to perform various operations on the
contents of the flash memory.
Changing Flash Protection Bits
As discussed in Section 7.2.2.2, changes to the protection bits must be committed before they
take effect. The sequence below is used change and commit a block protection bit in the FMPRE
or FMPPE registers. The sequence to change and commit a bit in software is as follows:
1. The Flash Memory Protection Read Enable (FMPRE) and Flash Memory Protection
Program Enable (FMPPE) registers are written, changing the intended bit(s). The action of
these changes can be tested by software while in this state.
2. The Flash Memory Address (FMA) register (see page 108) bit 0 is set to 1 if the FMPPE
register is to be committed; otherwise, a 0 commits the FMPRE register.
3. The Flash Memory Control (FMC) register (see page 111) is written with the COMT bit set.
This initiates a write sequence and commits the changes.
There is a special sequence to change and commit the DBG bits in the Flash Memory Protection
Read Enable (FMPRE) register. This sequence also sets and commits any changes from 1 to 0 in
the block protection bits (for execute-only) in the FMPRE register.
1. 1. The Flash Memory Protection Read Enable (FMPRE) register is written, changing the
intended bit(s). The action of these changes can be tested by software while in this state.
2. 2. The Flash Memory Address (FMA) register (see page 102) is written with a value of 0x900.
3. 3. The Flash Memory Control (FMC) register (see page 104) is written with the COMT bit set.
This initiates a write sequence and commits the changes.
Below is an example code sequence to permanently disable the JTAG and SWD interface to the
debug module using Luminary Micro's DriverLib peripheral driver library:
#include "hw_types.h"
#include "hw_flash.h"
void
permanently_disable_jtag_swd(void)
{
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April 27, 2007
Preliminary