LM3S102 Datasheet, PDF (51/335 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S102 Data Sheet
6.1.2.7
6.1.3
6.1.4
6.1.4.1
3. The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, and the first instruction designated by the program counter, and then
begins execution.
The watchdog reset timing is shown in Figure 18-13 on page 328.
Low Drop-Out
A reset can be made when the internal low drop-out (LDO) regulator output goes unregulated. This
is initially disabled and may be enabled by software. LDO is controlled with the LDO Power
Control (LDOPCTL) register (see page 65). The LDO reset sequence is as follows:
1. LDO goes unregulated and the LDOARST bit in the LDOARST register is set.
2. An internal reset is asserted.
3. The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, and the first instruction designated by the program counter, and then
begins execution.
The LDO reset timing is shown in Figure 18-14 on page 328.
Power Control
The LDO regulator permits the adjustment of the on-chip output voltage (V_OUT). The output may
be adjusted in 50 mV increments between the range of 2.25 V through 2.75 V. The adjustment is
made through the VADJ field of the LDO Power Control (LDOPCTL) register (see page 65).
Clock Control
System control determines the clocking and control of clocks in this part.
Fundamental Clock Sources
There are two fundamental clock sources for use in the device:
„ The main oscillator, driven from either an external crystal or a single-ended source. As a
crystal, the main oscillator source is specified to run from 1-8 MHz. However, when the crystal
is being used as the PLL source, it must be from 3.579545–8.192 MHz to meet PLL
requirements. As a single-ended source, the range is from DC to the specified speed of the
device.
„ The internal oscillator, which is an on-chip free running clock. The internal oscillator is
specified to run at 12 MHz ± 50%. It can be used to clock the system, but the tolerance of
frequency range must be met.
The internal system clock may be driven by either of the above two reference sources as well as
the internal PLL, provided that the PLL input is connected to a clock source that meets its AC
requirements.
Nearly all of the control for the clocks is provided by the Run-Mode Clock Configuration (RCC)
register (see page 74).
Figure 6-2 shows the logic for the main clock tree. The peripheral blocks are driven by the System
Clock signal and can be programmatically enabled/disabled.
October 6, 2006
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Preliminary