LM3S102 Datasheet, PDF (249/335 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S102 Data Sheet
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
Offset 0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TXRIS RXRIS RTRIS RORRIS
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Bit/Field
31:4
3
Name
reserved
TXRIS
2
RXRIS
1
RTRIS
0
RORRIS
Type
RO
RO
RO
RO
RO
Reset
0
1
0
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
SSI Transmit FIFO Raw Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
SSI Receive FIFO Raw Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
SSI Receive Time-Out Raw Interrupt Status
Indicates that the receive time-out has occurred, when set.
SSI Receive Overrun Raw Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
October 6, 2006
249
Preliminary