LM3S102 Datasheet, PDF (202/335 Pages) List of Unclassifed Manufacturers – Microcontroller

Universal Asynchronous Receiver/Transmitter (UART)
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If
the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared to 0 on reset.
UART Receive Status (UARTRSR): Read
Offset 0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
OE
BE
PE
FE
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
UART Error Clear (UARTECR): Write
Offset 0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DATA
Type
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
Name
Type
Reset Description
Read-Only Receive Status (UARTRSR) Register
31:4
reserved
RO
3
OE
RO
0
Reserved bits return an indeterminate value, and should never
be changed. The UARTRSR register cannot be written.
0
UART Overrun Error
When this bit is set to 1, data is received and the FIFO is already
full. This bit is cleared to 0 by a write to UARTECR.
The FIFO contents remain valid since no further data is written
when the FIFO is full, only the contents of the shift register are
overwritten. The CPU must now read the data in order to empty
the FIFO.
202
October 6, 2006
Preliminary