PS13201 Datasheet, PDF (5/22 Pages) List of Unclassifed Manufacturers – 500MHz 75dB Logarithmic/Limiting Amplifier

PS13201
The PS13201 consists of 6 Gain stages, 7 Detector stages, a limiting RF Output buffer and a Video Output amplifier.
The power supply connections to each section are isolated from each other to aid stability.
The PS13201 consumes 1.1W of power when ALL parts of the circuit are powered up from a ±5.0V power supply. As
the circuit uses a differential architecture, the power consumption of the RF gain/detector stages and RF Output Buffer
will be independent of RF input signal level. However, the Video Output (pin 13) is driven by a single ended emitter
follower and so the power consumption of the Video amplifier will vary with RF input signal level between pins 27 and
28.(upto 10mA over 2V video output range with max video load of 200Ω //20pF) The PS13201 has a high RF gain
(>50dB) across a wide bandwidth (>450MHz) when the limiting RF Output Buffer is enabled. The limiting RF Output Buffer
provides a balanced Limited Output level of nominally –1.0dBm on each RF Output connection (pin 9 and 10), for RF
input signal levels on pins 27 and 28 in excess of –50dBm.
The limiting RF Output Buffer can be isolated from the other sections of the PS13201, by disconnecting the RF Output
Buffer GND (pin 8) from 0V, and leave the pin floating. This feature aids stability in applications NOT requiring a Limited
RF Output signal, and lowers the power consumption of the PS13201 to 0.95Watts, when the other sections are
powered up from a ±5.0V power supply.
Each of the Gain and Detector stages has approximately 12dB of gain, and a significant amount of on-chip RF
decoupling (200pF per stage), also to aid stability. The Video amplifier provides a positive going output signal proportional
to the log of the amplitude of an RF input applied between pins 27 and 28. The gain and the offset of the Video amplifier
can be adjusted by 3 resistors; RG , RT , and RO which are connected to Gain adjust (pin 19),Trim reference (pin
18) and Offset adjust (pin 17). With RT set to 1.5k∧ , RG can be set to any value between 1kΩ and 2k2Ω and achieve a
range in Video Slope of ±20%, centred on 21mV/dB. Similarly, RO can be set to any value between 1kΩ and
2.2KΩ and achieve an offset range of ±0.5V, which should allow the Video Offset to be trimmed to 0V if required.
The RF input pins (27 and 28) have a 50Ω terminating resistor connected between them on–chip. These are
capacitively coupled to the I/P gain stage with 20pF on-chip capacitors. (Refer to APPLICATION NOTES section for
information on how to connect an RF input signal to the device).
Data Sheet 210892 issue 3
Plessey Semiconductors Ltd.
Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE
Tel: [phone]
Fax: [phone]
Web: www.plesseysemi.com
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