PS13201 Datasheet, PDF (10/22 Pages) List of Unclassifed Manufacturers – 500MHz 75dB Logarithmic/Limiting Amplifier

PS13201
A PRACTICAL APPLICATION FOR THE PS13201AS A LOG/LIMITING AMPLIFIER
The PS13201, with the RF Output-Buffer ENABLED, has a large limited RF Output level (0dBm on each of two RF
Output pins (9 and10)) and a wide RF bandwidth (450MHz) in a small 28 pin Miniature Ceramic S.O package. As a
result, there is a tendency for the device to become unstable unless care is used in the application.
The PCB layout for a ”PS13201 DEMONSTRATION BOARD” in Fig. 11 has proved reliably stable. The PCB is a
double layer Fibre epoxy board which uses SMDs where possible. A circuit diagram for the Demonstration PCB
appears in Fig. 10.
The following points should be noted when this application is realised practically:-
1. A wire needs to connect the two pads connected to pins 14 and 15 of the PS13201, to allow +5V to appear at
both pins.
2. ALL the GND connections to the PS13201 are made through the PCB to a Ground plane on the bottom side.
It is important to ensure that the impedance of each of these connections is kept to an absolute
minimum to prevent instability. If these connections are achieved using through plated holes, it is
recommended that they are filled with solder to lower their impedance.
3. The PCB is configured to accept SMA, SMB or SMC connectors for the RF input, RF Output and Video
Output connections. These can be changed if necessary to an alternative type, but it is vital to ensure
that the ground plane is solidly connected to the Guard Ring which surrounds the RF Output tracks.
4. The PCB is configured to accept a small surface mounting DC isolating BALUN transformer (e.g
VANGUARD VE43666, available from Vanguard Electronics Company Inc, 1480 West 178th St.
GARDENA, C.A. 90248, U.S.A. Tel:- U.S.A. (213) 323 – 4100) to couple a signal into the RF input
connections (pins 27 and 28). It is NOT recommended to attempt operating the PS13201 with the RF
Output Buffer enabled, WITHOUT using an input BALUN, although it may be possible, provided the input
source impedance to both pins 27 and 28 remains balanced. The centre tap of the secondary winding of the
transformer should be soldered to the small ground plane on the upper side of the PCB.
5. The RF Output connection to the PCB is from pin 9 of the PS13201 only, with pin 10 being terminated on
the PCB using a 510 resistor. It is important to ensure that both pin 9 and10 are terminated with equal
impedances.
6. The RF Output Buffer can be enabled by soldering a link (LK) between pin 8 of the PS13201 and the
adjacent guard track around the RF Output lines. Similarly, the buffer can be disabled by removing the same
link. When the buffer is disabled, the following components can be omitted:-
7. 1nF capacitors (C1, C2)
8. 10nF capacitor (C8)
9. 510 resistor (RFO )
10. The Slope (gain) and Offset of the Video Output can be adjusted using two 1Kω trimmers, provision for
which is included in the PCB layout.
11. The plots in Fig. 12 to fig. 23 are typical of the performance of PS13201 devices used with the PCB layout
detailed in Fig.11.
Data Sheet 210892 issue 3
Plessey Semiconductors Ltd.
Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE
Tel: [phone]
Fax: [phone]
Web: www.plesseysemi.com
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