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N3292X Datasheet, PDF (5/8 Pages) List of Unclassifed Manufacturers – ARM926EJ-S 32-bit RISC CPU with 8KB I-Cache & 8KB D-Cache
N3292x Brief
 Support OSD functions to overlap system information like battery life, brightness tuning, volume tuning or
muting, etc.
 SPU (Sound Processing Unit)
 7-bit volume control supported for each of 32 channels
 5-bit pan control supported for each L/R of 32 channels
 10-band equalizer supported
 Special code supported for loop playing and event detection
 AAC accelerator
 MDCT/IMDCT engine
 I2S Controller
 I2S interface supported to connect external audio codec
 16/18/20/24-bit data format supported
 Storage Interface Controller
 Interface to NAND Flash:
 8-bit data bus width supported
 SLC and MLC type NAND Flash supported
 512B, 2KB, 4KB, and 8KB page size NAND Flash supported
 ECC24 algorithm supported for ECC generation, error detection and error correction
 PBA-NAND flash supported
 Interface to SD/MMC/SDIO/SDHC/micro-SD cards supported
 SD-to-NAND flash bridge supported
 DMA function supported to accelerate the data transfer between system memory and NAND Flash or
SD/MMC/SDIO/SDHC/micro-SD
 USB Device Controller
 USB2.0 HS (High-Speed) x 1 port
 6 configurable endpoints supported
 Control, Bulk, Interrupt and Isochronous transfers supported
 Suspend and remote wakeup supported
 USB Host Controllers
 One USB 1.1 Host port
 One USB 2.0 Host port
 Over Current detection required
 Fully compliant with USB Revision 1.1 and 2.0 specifications
 Open Host Controller Interface (OHCI) Revision 1.0 compatible
 High-speed (480Mbps), Full-speed (12Mbps) and low-speed (1.5Mbps) USB devices supported
 Control, Bulk, Interrupt and Isochronous transfers supported
 Timer & Watch-Dog Timer
 Four 32-bit with 8-bit pre-scalar timers supported
 One programmable 24-bit Watch-Dog Timer supported
 PWM
 4 PWM channel outputs supported
 16-bit counter supported for each PWM channel
 Two 8-bit pre-scalars supported and each pre-scalar shared by two PWM channels
 Two clock-dividers supported and each divider shared by two PWM channels
Nuvoton Technology Corp.
http://www.nuvoton.com/
-5-
Release Date: Feb. 2014
Revision A3