ISD9160 Datasheet, PDF (5/23 Pages) List of Unclassifed Manufacturers – ISD Cortex-M0 ChipCorder

ISD9160 Datasheet
– Input selectable from dedicated MIC pins or analog enabled GPIO.
– Programmable biquad filter to support multiple sample rates from 8-32kHz.
– DMA support for minimal CPU intervention.
• Differential Audio PWM Output (DPWM)
– Direct connection of speaker
– 1W drive capability into 8Ω load.
– High efficiency 88%
– Configurable up-sampling to support sample rates from 8-32kHz.
– DMA support for minimal CPU intervention.
• Timers
– Two timers with 8-bit pre-scaler and 24-bit resolution.
– Counter auto reload.
• Watch Dog Timer
– Default ON/OFF by configuration setting
– Multiple clock sources
– 8 selectable time out period from micro seconds to seconds (depending on clock source)
– WDT can wake up power down/sleep.
– Interrupt or reset selectable on watchdog time-out.
• RTC
– Real Time Clock counter (second, minute, hour) and calendar counter (day, month, year)
– Alarm registers (second, minute, hour, day, month, year)
– Selectable 12-hour or 24-hour mode
– Automatic leap year recognition
– Time tick and alarm interrupts.
– Device wake up function.
– Supports software compensation of crystal frequency by compensation register (FCR)
• PWM/Capture
– Built-in up to two 16-bit PWM generators provide two PWM outputs or one complementary
paired PWM outputs.
– The PWM generator equipped with a clock source selector, a clock divider, an 8-bit pre-scaler
and Dead-Zone generator for complementary paired PWM.
– PWM interrupt synchronous to PWM period.
– 16-bit digital Capture timers (shared with PWM timers) provide rising/falling capture inputs.
– Support Capture interrupt
• UART
– UART ports with flow control (TX, RX, CTS and RTS)
– 8-byte FIFO.
– Support IrDA (SIR) and LIN function
– Programmable baud-rate generator up to 1/16 of system clock.
• SPI
– Master up to 20 Mbps / Slave up to 10 Mbps.
– Support MICROWIRE/SPI master/slave mode (SSP)
– Full duplex synchronous serial data transfer
– Variable length of transfer data from 1 to 32 bits
– MSB or LSB first data transfer
– 2 slave/device select lines when used in master mode.
– Hardware CRC calculation module available for CRC calculation of data stream.
– DMA support for burst transfers.
• I2C
– Master/Slave up to 1Mbit/s
– Bidirectional data transfer between masters and slaves
– Multi-master bus (no central master).
Release Date: Oct 29, 2011
-5-
Revision V1.20