C5001 Datasheet, PDF (5/13 Pages) List of Unclassifed Manufacturers – Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG.

C5001
Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG.
Approved Product
Application Note for Selection on Bi-Directional Pins
Pins 10, 11, 14, 15, 18, 19, 22, 23, 26 and 27 are Power
up bi-directional pins and are used for selecting power
up output frequencies of this devices output clocks (see
Pin description, Page 2). During power-up of the device,
these pins are in input mode, therefore, they are
considered input select pins internal to the IC, these
pins have a large value pull-up each (250KΩ), therefore,
a selection “1” is the default and will select a 66 MHz
output frequency. If the system uses a slow power
supply (over 5 ms settling time), then it is recommended
to use an external pull-up (Rup) in order to insure a high
selection. In this case, the designer may choose one of
two configurations, see FIG. 3A and Fig. 3B.
Fig. 3A represents an additional pull up resistor 50KΩ
connected from the pin to the power line, which allows a
faster pull to a high level.
If a selection “0” is desired, then a jumper is placed on
JP1 to a 5KΩ resistor as implemented as shown in Fig.
3A. Please note the selection resistors (Rup and Rdn)
are placed before the Damping resistor (Rd) close to
the pin.
C5001
Bidirectional
Vdd
Rup
50K
Rd
Load
JP1
JUMPER
Rdn
5K
Fig.3A
Vdd ^JP2
3 Way Jumper
Fig. 3B represents a single resistor 10KΩ connected to
a 3-way jumper, JP2. When a “1” selection is desired, a
Rsel
jumper is placed between leads 1 and 3. When a “0”
C5001
10K
selection is desired, a jumper is placed between leads 1
and 2.
Bidirectional
Rd
Load
If the system power supply is fast (less than 5 mSec
settling time), then Fig. 3A only applies and Pull up Rup
resistor is not necessary.
Fig.3B
The electrical length of the trace that connects the
selection resistor to the devices pin should be kept as
short as possible.
Input and Output Relationships
The device acts a PCI clock generator. Output clocks may be individually controlled to be either 33.3 or 66.6 MHz in
frequency by setting or clearing the clocks respective I²C control register bit. All output clocks are rising edge aligned to
within a shared 500 pS window. There is no specified relationship between the input reference clock and the output
clocks.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: [phone]. FAX [phone]
Rev.2.1
6/14/1999
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