C5001 Datasheet, PDF (1/13 Pages) List of Unclassifed Manufacturers – Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG.

C5001
Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG.
Approved Product
Product Features
S Produces PCI output clocks that are individually
selectable for 33.3 or 66.6 MHz under I²C or
strapping control.
S Separate output buffer power supply for reduced
noise, crosstalk and jitter.
S input clock frequency standard 14.31818 MHz
S Output clocks frequency individually selectable via
I²C or hardware bi-directional pin strapping.
S SSCG EMI reduction at 1.0% width
S Individual clock disables via I²C control
S All output clocks skewed within a 500 pS window
S Cycle to Cycle jitter ± 250 pS
S Output duty cycle is automatically 50% (±10%)
adjusted
S Clock feed through mode and OE pins for logic
testing
S Glitchless clock enabling and disabling transitions
S 28-pin TSSOP or SSOP package
Block Diagram
XIN
XOUT
Reference
Oscillator
÷1 ÷2
÷1 ÷2
M
U
REF-
X
CLK0/S0
CLK1/S1
PLL
÷1 ÷2
÷1 ÷2
CLK2/S2
CLK3/S3
÷1 ÷2
CLK4/S4
÷1 ÷2
CLK5/S5
÷1 ÷2
CLK6/S6
÷1 ÷2
CLK7/S7
÷1 ÷2
CLK8/S8
Output Enable logic Functionality Table
OE
CLK(0:9)
PLL
1 (HIGH)
Enabled
Running
0 (LOW)
Tri State
Running
Pin Configuration
VDD 1
XIN 2
XOUT 3
VSS 4
OE 5
SCLK 6
SDATA 7
VSS 8
VSS 9
CLK9/S9 10
CLK8/S8 11
VDD5 12
VSS 13
CLK7/S7 14
28 VDD1
27 REF-CLK0/S0
26 CLK1/S1
25 VSS
24 VDD2
23 CLK2/S2
22 CLK3/S3
21 VSS
20 VDD3
19 CLK4/S4
18 CLK5/S5
17 VSS
16. VDD4
15 CLK6/S6
OE
SDATA
SCLK
I2C
LOGIC
÷1 ÷2
÷4, ÷8
CLK9/S9
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: [phone]. FAX [phone]
Rev. 2.1
6/14/1999
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