MK02FN128VLH10 Datasheet, PDF (45/56 Pages) List of Unclassifed Manufacturers – 100 MHz Cortex-M4 Based Microcontroller with FPU

Peripheral operating requirements and behaviors
6. A Fast mode I²C bus device can be used in a Standard mode I2C bus system, but the requirement t_{SU; DAT} ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t_rmax
+ t_{SU; DAT} = 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification) before the SCL line is
released.
7. C_b = total capacitance of the one bus line in pF.
Table 36. I ²C 1 Mbps timing
Characteristic
SCL Clock Frequency
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time for I₂C bus devices
Data set-up time
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
Bus free time between STOP and START
condition
Pulse width of spikes that must be suppressed by
the input filter
Symbol
f_SCL
t_HD; STA
t_LOW
t_HIGH
t_SU; STA
t_HD; DAT
t_SU; DAT
t_r
t_f
t_SU; STO
t_BUF
t_SP
Minimum
0
0.26
0.5
0.26
0.26
0
50
20 +0.1C_b, ²
20 +0.1C_b2
0.26
0.5
0
Maximum
1¹
—
—
—
—
—
—
120
120
—
—
50
Unit
MHz
 ^µs
 ^µs
µs
µs
µs
ns
ns
ns
µs
µs
ns
1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins
across the full voltage range.
2. C_b = total capacitance of the one bus line in pF.
SDA
t_f
t_LOW
t_r
t_{SU; DAT}
t_f
t_{HD; STA}
t_SP
t_r
t_BUF
SCL
S
HD; STA
t_{HD; DAT}
t_HIGH
t_{SU; STA}
SR
t_{SU; STO}
P
S
Figure 22. Timing definition for devices on the I²C bus
3.8.4 UART switching specifications
See General switching specifications.
Kinetis K02 64 KB/128 KB Flash, Rev. 3, 4/2015
45
Freescale Semiconductor, Inc.