MK02FN128VLH10 Datasheet, PDF (17/56 Pages) List of Unclassifed Manufacturers – 100 MHz Cortex-M4 Based Microcontroller with FPU

General
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and timers.
Table 9. General switching specifications
Symbol
Description
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
External RESET and NMI pin interrupt pulse width —
Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, passive filter disabled) — Asynchronous
path
Port rise and fall time
• Slew disabled
• 1.71 ≤ V_DD ≤ 2.7V
• 2.7 ≤ V_DD ≤ 3.6V
• Slew enabled
• 1.71 ≤ V_DD ≤ 2.7V
• 2.7 ≤ V_DD ≤ 3.6V
Min.
1.5
100
50
—
—
—
—
Max.
—
—
—
Unit
Bus clock
cycles
ns
ns
Notes
1, 2
3
4
5
10
ns
5
ns
30
ns
16
ns
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can
be recognized in that case.
2. The greater of synchronous and asynchronous timing must be met.
3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
5. 25 pF load
2.4 Thermal specifications
Kinetis K02 64 KB/128 KB Flash, Rev. 3, 4/2015
17
Freescale Semiconductor, Inc.