AT45DB321E Datasheet, PDF (44/72 Pages) List of Unclassifed Manufacturers – 32-Mbit DataFlash (with Extra 1-Mbits), 2.3V Minimum SPI Serial Flash Memory

16.
Power-On/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI
Mode 3. In addition, the output pin (SO) will be in a high impedance state, and a high-to-low transition on the CS pin will
be required to start a valid instruction. The SPI mode (Mode 3 or Mode 0) will be automatically selected on every falling
edge of CS by sampling the inactive clock state.
16.1
Initial Power-Up Timing Restrictions
During power-up, the device must not be accessed for at least the minimum t_VCSL time after the supply voltage reaches
the minimum V_CC level. While the device is being powered-up, the internal Power-On Reset (POR) circuitry keeps the
device in a reset mode until the supply voltage rises above the maximum POR threshold value (V_POR). During this time,
all operations are disabled and the device will not respond to any commands. After power-up, the device will be in the
standby mode.
If the first operation to the device after power-up will be a program or erase operation, then the operation cannot be
started until the supply voltage reaches the minimum V_CC level and an internal device delay has elapsed. This delay will
be a maximum time of t_PUW.
Table 16-1. Power-Up Timing
Symbol
t_VCSL
t_PUW
V_POR
Parameter
Minimum V_CC to Chip Select Low Time
Power-Up Device Delay Before Program or Erase Allowed
Power-On Reset (POR) Voltage
Min
Max
Units
85
μs
3
ms
1.5
2.2
V
Figure 16-1. Power-Up Timing
V_CC
V_CC (min)
V_POR (max)
V_POR (min)
Do Not Attempt
Device Access
During this Time
t_VCSL
t_PUW
Read Operation Permitted
Program/Erase Operations Permitted
Time
AT45DB321E 44
8784E–DFLASH–10/2013