W77L532A Datasheet, PDF (43/88 Pages) List of Unclassifed Manufacturers – 8-BIT MICROCONTROLLER

W77L532A
10. RESET CONDITIONS
The user has several hardware related options for placing the W77L532 into reset condition. In general,
most register bits go to their reset value irrespective of the reset condition, but there are a few flags
whose state depends on the source of reset. The user can use these flags to determine the cause of
reset using software. There are two ways of putting the device into reset state. They are External reset
and Watchdog reset.
External Reset
The device continuously samples the RST pin at state C4 of every machine cycle. Therefore the RST
pin must be held for at least 2 machine cycles to ensure detection of a valid RST high. The reset
circuitry then synchronously applies the internal reset signal. Thus the reset is a synchronous operation
and requires the clock to be running to cause an external reset.
Once the device is in reset condition, it will remain so as long as RST is 1. Even after RST is
deactivated, the device will continue to be in reset state for up to two machine cycles, and then begin
program execution from 0000h. There is no flag associated with the external reset condition. However
since the other two reset sources have flags, the external reset can be considered as the default reset if
those two flags are cleared.
The software must clear the POR flag after reading it, otherwise it will not be possible to correctly
determine future reset sources. If the power fails, i.e. falls below Vrst, then the device will once again go
into reset state. When the power returns to the proper operating levels, the device will again perform a
power on reset delay and set the POR flag.
Watchdog Timer Reset
The Watchdog timer is a free running timer with programmable time-out intervals. The user can clear
the watchdog timer at any time, causing it to restart the count. When the time-out interval is reached an
interrupt flag is set. If the Watchdog reset is enabled and the watchdog timer is not cleared, then 512
clocks from the flag being set, the watchdog timer will generate a reset . This places the device into the
reset condition. The reset condition is maintained by hardware for two machine cycles. Once the reset
is removed the device will begin execution from 0000h.
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Publication Release Date: December 4, 2008
Revision A10