M054ZBN Datasheet, PDF (36/68 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

NuMicro^™ M052/M054BN Data Sheet
6.4.1.3 Open-Drain Mode Explanation
Set Px_PMD(PMDn[1:0]) to 2‟b10 the Px[n] pin is in Open-Drain mode and the I/O pin supports
digital output function but only with sink current capability, an additional pull-up resister is needed
for driving high state. If the bit value in the corresponding bit [n] of Px_DOUT is “0”, the pin drive a
“low” output on the pin. If the bit value in the corresponding bit [n] of Px_DOUT is “1”, the pin
output drives high that is controlled by the internal pull-up resistor or the external pull high
resistor.
Port Latch
N
Data
Port Pin
Input Data
Figure 6-11 Open-Drain Output
6.4.1.4 Quasi-bidirectional Mode Explanation
Set Px_PMD(PMDn[1:0]) to 2‟b11 the Px[n] pin is in Quasi-bidirectional mode and the I/O pin
supports digital output and input function at the same time but the source current is only up to
hundreds uA. Before the digital input function is performed the corresponding bit in Px_DOUT
must be set to 1. The quasi-bidirectional output is common on the 80C51 and most of its
derivatives. If the bit value in the corresponding bit [n] of Px_DOUT is “0”, the pin drive a “low”
output on the pin. If the bit value in the corresponding bit [n] of Px_DOUT is “1”, the pin will check
the pin value. If pin value is high, no action takes. If pin state is low, then pin will drive strong high
with 2 clock cycles on the pin and then disable the strong output drive and then the pin status is
control by internal pull-up resistor. Note that the source current capability in quasi-bidirectional
mode is only about 200uA to 30uA for V_DD is form 5.0V to 2.5V
VDD
Port Latch
Data
2 CPU
Clock Delay
P _Strong P
Very
Weak
P _Weak
N
Port Pin
Input Data
Figure 6-12 Quasi-bidirectional I/O Mode
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Publication Release Date: Mar. 19, 2012
Revision V1.01