M054ZBN Datasheet, PDF (33/68 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

NuMicro^™ M052/M054BN Data Sheet
6.3.6 Power Down Mode (Deep Sleep Mode) Clock
When chip enter into power down mode, most of clock sources, peripheral clocks and system
clock will be disabled directly. Internal 10kHz could be still active in power down/deep power
down mode if CPU does not disable it before entering power down mode. IP engine clock could
be still active in power down/deep power down mode if IP adopts internal 10kHz does not be
disabled respectively.
6.3.7 Frequency Divider Output
This device is equipped a power-of-2 frequency divider which is composed by 16 chained divide-
by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is
reflected to P3.6. Therefore there are 16 options of power-of-2 divided clocks with the frequency
from F_in/2¹ to F_in/2¹⁷ where Fin is input clock frequency to the clock divider.
The output formula is F_out = F_in/2^(N+1), where F_in is the input clock frequency, F_out is the clock
divider output frequency and N is the 4-bit value in FREQDIV.FSEL[3:0].
When write 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When write 0 to
DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low
state and stay in low state.
22.1184 MHz
11
HCLK
10
Reserved
01
4~24 MHz
00
FRQDIV_S (CLKSEL2[3:2])
FDIV_EN(APBCLK[6])
FRQDIV_CLK
Figure 6-8 Clock Source of Frequency Divider
- 33 -
Publication Release Date: Mar. 19, 2012
Revision V1.01