KXTI9-1001 Datasheet, PDF (33/54 Pages) List of Unclassifed Manufacturers – 2g/4g/8g Tri-axis Digital Accelerometer Specifications

± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KXTI9-1001
Rev. 2
Jul-2011
TDT_TOTAL_TIMER
This register contains counter information for the detection of a double tap event. When the Directional
Tap^TM ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the Directional
Tap^TM ODR is 800Hz, every count is calculated as 2/ODR delay period. When the Directional Tap^TM
ODR is 1600Hz, every count is calculated as 4/ODR delay period. The Directional Tap^TM ODR is user-
defined per Table 15. In order to ensure that only tap events are detected, this time limit is used. This
register sets the total amount of time that the two taps in a double tap event can be above the PI
threshold (TDT_L_THRESH). The Kionix recommended default value for TDT_TOTAL_TIMER is 0.09
seconds (0x24h). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1
must first be set to “0”.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STD7
STD6
STD5
STD4
STD3
STD2
STD1
STD0
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
I²C Address: 0x2Fh
00100100
TDT_LATENCY_TIMER
This register contains counter information for the detection of a tap event. When the Directional Tap^TM
ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the Directional Tap^TM
ODR is 800Hz, every count is calculated as 2/ODR delay period. When the Directional Tap^TM ODR is
1600Hz, every count is calculated as 4/ODR delay period. The Directional Tap^TM ODR is user-defined
per Table 15. In order to ensure that only tap events are detected, this time limit is used. This register
sets the total amount of time that the tap algorithm will count samples that are above the PI threshold
(TDT_L_THRESH) during a potential tap event. It is used during both single and double tap events.
However, reporting of single taps on the physical interrupt pin (7) will occur at the end of the
TDT_WINDOW_TIMER. The Kionix recommended default value for TDT_LATENCY_TIMER is 0.1
seconds (0x28h). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1
must first be set to “0”.
R/W
TLT7
Bit7
R/W
TLT6
Bit6
R/W
TLT5
Bit5
R/W
TLT4
Bit4
R/W
TLT3
Bit3
R/W
TLT2
Bit2
R/W
R/W
TLT1
TLT0
Bit1
Bit0
I²C Address: 0x30h
Reset Value
00101000
TDT_WINDOW_TIMER
This register contains counter information for the detection of single and double taps. When the
Directional Tap^TM ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the
Directional Tap^TM ODR is 800Hz, every count is calculated as 2/ODR delay period. When the
Directional Tap^TM ODR is 1600Hz, every count is calculated as 4/ODR delay period. The Directional
Tap^TM ODR is user-defined per Table 15. It defines the time window for the entire tap event, single or
double, to occur. Reporting of single taps on the physical interrupt pin (7) will occur at the end of this
tap window. The Kionix recommended default value for TDT_WINDOW_TIMER is 0.4 seconds
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