KXTI9-1001 Datasheet, PDF (31/54 Pages) List of Unclassifed Manufacturers – 2g/4g/8g Tri-axis Digital Accelerometer Specifications

± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KXTI9-1001
Rev. 2
Jul-2011
defined per Table 15. TDT_TIMER represents the minimum time separation between the first tap and
the second tap in a double tap event. The Kionix recommended default value is 0.3 seconds (0x78h).
Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to
“0”.
R/W
TDTC7
Bit7
R/W
TDTC6
Bit6
R/W
TDTC5
Bit5
R/W
TDTC4
Bit4
R/W
TDTC3
Bit3
R/W
R/W
R/W
TDTC2 TDTC1 TDTC0
Bit2
Bit1
Bit0
I²C Address: 0x2Bh
Reset Value
01111000
TDT_H_THRESH
This register represents the 8-bit jerk high threshold to determine if a tap is detected. Though this is an
8-bit register, the KXTI9 internally multiplies the register value by two in order to set the high threshold.
This multiplication results in a range of 0d to 510d with a resolution of two counts. The Performance
Index (PI) is the jerk signal that is expected to be less than this threshold, but greater than the
TDT_L_THRESH threshold during single and double tap events. Note that to properly change the
value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. The Kionix recommended
default value is 203 (0xCBh) and the Performance Index is calculated as:
X‟ = X(current) – X(previous)
Y‟ = Y(current) – Y(previous)
Z‟ = Z(current) – Z(previous)
PI = |X‟| + |Y‟| + |Z‟|
Equation 1. Performance Index
R/W
TTH7
Bit7
R/W
TTH6
Bit6
R/W
TTH5
Bit5
R/W
TTH4
Bit4
R/W
TTH3
Bit3
R/W
R/W
R/W
TTH2
TTH1
TTH0
Bit2
Bit1
Bit0
I²C Address: 0x2Ch
Reset Value
11001011
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