MC3413 Datasheet, PDF (31/47 Pages) List of Unclassifed Manufacturers – Axis Accelerometer

MC3413 3-Axis Accelerometer
Preliminary Datasheet
11.4 INTEN INTERRUPT ENABLE REGISTER
The interrupt enable register allows the flag bits for specific TAP and sample events to also
trigger a transition of the external INTN pin. This is the only effect these bits have as the flag
bits will be set/cleared in the SR Status Register regardless of which interrupts are enabled in
this register.
Addr
0x06
Name Description
Bit 7 Bit 6
INTEN
Interrupt Enable ACQ_INT_
Register
EN
Resv
Bit 5
TIZNEN
Bit 4
TIZPEN
Bit 3 Bit 2
TIYNEN TIYPEN
Bit 1 Bit 0
TIXNEN TIXPEN
POR R/
Value W
0x00 W
TIXPEN
TIXNEN
TIYPEN
TIYNEN
TIZPEN
TIZNEN
ACQ_INT_EN
Positive X-axis TAP interrupt enable
0: Disabled (default)
1: Enabled. The corresponding TAP enable bit in register 0x09 must be enabled.
The INTN pad will transition.
Negative X-axis TAP interrupt enable
0: Disabled (default)
1: Enabled. The corresponding TAP enable bit in register 0x09 must be enabled.
The INTN pad will transition.
Positive Y-axis TAP interrupt enable
0: Disabled (default)
1: Enabled. The corresponding TAP enable bit in register 0x09 must be enabled.
The INTN pad will transition.
Negative Y-axis TAP interrupt enable
0: Disabled (default)
1: Enabled. The corresponding TAP enable bit in register 0x09 must be enabled.
The INTN pad will transition.
Positive Z-axis TAP interrupt enable
0: Disabled (default)
1: Enabled. The corresponding TAP enable bit in register 0x09 must be enabled.
The INTN pad will transition.
Negative Z-axis TAP interrupt enable
0: Disabled (default)
1: Enabled. The corresponding TAP enable bit in register 0x09 must be enabled.
The INTN pad will transition.
Generate Interrupt
0: Disable automatic interrupt on INTN pad after each sample (default).
1: Enable automatic interrupt on INTN pad after each sample.
Table 14. INTEN Interrupt Enable Register Settings
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APS-048-0029v1.7
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