RFM219SW Datasheet, PDF (30/35 Pages) List of Unclassifed Manufacturers – Wireless Alarm and Security Systems

RFM219SW
This interrupt is generated when the preamble validation is passed and
4
r PREAM_PS_FLG the PREAM_PS_EN is set to 1. It can be cleared by setting the
PREAM_PS_CLR to 1.
This interrupt is generated when the sync word validation is passed and
3
r SYNC_PS_FLG
the SYNC_PS_EN is set to 1. It can be cleared by setting the
SYNC_PS_CLR to 1.
This interrupt is generated when the node ID validation is passed in the
2
r NODE_PS_FLG packet mode and the NODE_PS_EN is set to 1. It can be cleared by
setting the NODE_PS_CLR to 1.
This interrupt is generated when the CRC validation is passed in the
1
r CRC_PS_FLG
packet mode and the CRC_PS_EN is set to 1. It can be cleared by
setting the CRC_PS_CLR to 1.
This interrupt is generated when a packet is received (regardless of the
0
r PKT_DONE_FLG CRC validation) in the packet mode and the PKT_DONE_EN is set to 1.
It can be cleared by setting the PKT_DONE_CLR to 1.
Table 22. INTCTL_D
Register Bit RW
Bit Name
Descriptions
7
r RESV
This bit is reserved.
This interrupt is generated in the FIFO Mode and Packet Mode. The flag
6
r FIFO_FULL_FLG goes high when the FIFO is full. It is cleared automatically when the
FIFO is not full.
This interrupt is generated in the FIFO Mode and Packet Mode. The flag
goes high when the FIFO is found to be not empty (the number of
5
r FIFO_NMTY_FLG
unread data byte is not zero). It is cleared automatically when the FIFO
is empty.
INTCTL_D 4
(0x44)
r FIFO_TH_FLG
This interrupt is generated in the FIFO Mode and Packet Mode. The flag
goes high when the number of unread data bytes reaches/exceeds the
value defined in the “FIFO Threshold” parameter. It is cleared
automatically when the number of unread data bytes is less than the
“FIFO Threshold”.
This interrupt is generated in the FIFO Mode and Packet Mode. The flag
3
r FIFO_OVF_FLG goes high when the FIFO is overflow. It is cleared automatically when
the FIFO is not overflow.
2 w FIFO_PKT_CLR
1 r/w RESV
0: Keep the FIFO content (default).
1: Clear the FIFO content.
Note: This bit only takes effect in the STBY, TUNE, RX and EEPROM
state. In the SLEEP state, the FIFO and packet handler is automatically
cleared and reset.
Must always set to 0.
0 r/w RESV
Must always set to 0.
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