RFM219SW Datasheet, PDF (29/35 Pages) List of Unclassifed Manufacturers – Wireless Alarm and Security Systems

RFM219SW
The details of each interrupt are introduced in the registers INTCTL_B,
INTCTL_C and INTCTL_D.
The FIFO_WBYTE is the FIFO write-byte strobe that pulses up when
each byte is filled into the FIFO. Because it is a pulse, It cannot be seen
in the INTCTL_C register which reflects the interrupt flags.
3:0 r/w INT1_CTL<3:0>
This allows the user to select which interrupt is observable on the INT1.
The interrupt mapping is identical to that of the INT2.
Table 20. INTCTL_B
Register Bit RW
Bit Name
Descriptions
7 w SL_TMO_CLR
6 w RX_TMO_CLR
0: Keep the sleep timer timeout interrupt (default).
1: Clear the sleep timer timeout interrupt.
0: Keep the receive timer timeout interrupt (default).
1: Clear the receive timer timeout interrupt.
0: Keep the RSSI valid interrupt (default).
5 w RSSI_VLD_CLR
1: Clear the RSSI valid interrupt.
4
INTCTL_B^[1]
(0x42)
3
0: Keep the preamble detection pass interrupt (default).
w PREAM_PS_CLR
1: Clear the preamble detection pass interrupt.
w SYNC_PS_CLR
0: Keep the sync word detection pass interrupt (default).
1: Clear the sync word detection pass interrupt.
0: Keep the node ID detection pass interrupt (default).
2 w NODE_PS_CLR
1: Clear the node ID detection pass interrupt.
1 w CRC_PS_CLR
0: Keep the CRC validation pass interrupt (default).
1: Clear the CRC validation pass interrupt.
0: Keep the packet receive finish interrupt (default).
0 w PKT_DONE_CLR
1: Clear the packet receive finish interrupt.
Note:
[1]. Every bit in this register only takes effect in STBY, TUNE, RX and EEPROM state.
Table 21. INTCTL_C
Register Bit RW
Bit Name
7
r SL_TMO_FLG
INTCTL_C 6
(0x43)
r RX_TMO_FLG
5
r RSSI_VLD_FLG
Descriptions
This interrupt is generated when the sleep timer is turned on and the
SL_TMO_EN is set to 1. The flag goes high at the sleep timer timeout. It
can be cleared by setting the SL_TMO_CLR to 1.
This interrupt is generated when the receive timer is turned on and the
RX_TMO_EN is set to 1. The flag goes high at the receive timer timeout.
It can be cleared by setting the RX_TMO_CLR to 1.
This interrupt is generated when (G)FSK demodulation is used and the
RSSI_VLD_EN is set to 1. The flag goes high when the RSSI exceeds
the FSK Trigger Threshold. It can be cleared by setting the
RSSI_VLD_CLR to 1.
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