CME6005 Datasheet, PDF (3/16 Pages) List of Unclassifed Manufacturers – Single and dual band receiver IC

Preliminary Data Sheet CME6005 C-MAX
6- Pad Layout
Pin Layout SSO16
QC 13
QIN
1
GND
2
QOUT
3
VCC
4
IN 2
5
IN 1
6
Y-axis
X-axis
Reference point (%)
12 DEM
11 HLD
10 PK
9 PON
8 TCO
7
TCON
Figure 2. Pad layout
Th e PA D co or d in a te s
are referred to the left
bottom point of the contact
window
QC ¹
16 NC
QIN ²
15 _DEM
GND ³
14 _HLD
QOUT ⁴ _CME6005 ¹³ PK
VCC ⁵
FB
12 _PON
IN 2 ⁶
11 _TCO
IN 1 ⁷
10 _TCON
NC ⁸
9 NC
Figure 3. Pin layout SSO16
PIN Description
IN1, IN2
A ferrite antenna is connected between IN 1 and IN 2. For high sensitivity, the Q factor of the antenna circuit
should be as high as possible. Please note that a high Q factor requires temperature compensation of the
resonant frequency in most cases. We recommend a Q factor between 40 and 150, depending on the
application. An optimal signal-to-noise ratio will be achieved by a resonator resistance of 40 kΩ to 100 kΩ.
QOUT, QIN , QC
In order to achieve a high selectivity, a crystal is connected between the Pins QOUT and QIN. It is used with
the serial resonant frequency according to the time-code transmitter and acts as a serial resonator. Up to 2
crystals can be connected parallel between QOUT and QIN. For one crystal, the given parallel capacitor of
the filter crystal (about 1.4 pF) is internally compensated so that the bandwidth of the filter is about 10 Hz.
For two crystals, an additional external capacitor with the value of about 1.4 pF has to be connected parallel
between QC and QIN. The impedance of QIN is high. Parasitic loads have to be avoided.
DEM
Demodulator output. To ensure the function, an external capacitor has to be connected at this output.
HLD
AGC hold mode: HLD high (V_HLD = V_CC) sets normal function, HLD low (V_HLD = 0) holds for a short time the
AGC voltage. This can be used to prevent the AGC from peak voltages, created by e.g. a stepper motor
PK
Peak detector output. An external capacitor has to be connected to ensure the function of the AGC
regulation. The value of the capacitance influences the AGC regulation time.
NOTE: To realize a good regulation timing of the demodulator and the peak detector the value of the
capacitors at DEM and PK have to be changed for the different protocols.
SPEC No.
CME6005
Revision
A.7
State
07.12.04
C-MAX printed
07.12.2004
Version
English
Page
3 of 16