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591BD-DDG Datasheet, PDF (3/12 Pages) List of Unclassifed Manufacturers – 1 ps MAX JITTER CRYSTAL OSCILLATOR (XO) (10 MHZ TO 810 MHZ) | |||
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Si590/591
Table 3. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option1
LVDS Output Option2
Symbol
VO
VOD
VSE
VO
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
Min
VDD â 1.42
1.1
0.55
1.125
Typ
â
â
â
1.20
Max Units
VDD â 1.25 V
1.9
VPP
0.95
VPP
1.275
V
VOD
swing (diff)
0.5
0.7
0.9
VPP
CML Output Option2
2.5/3.3 V option mid-level
VO
1.8 V option mid-level
â
VDD â 1.30
â
â
VDD â 0.36
â
V
2.5/3.3 V option swing (diff) 1.10
VOD
1.8 V option swing (diff)
0.35
1.50
0.425
1.90
0.50
VPP
CMOS Output Option3
VOH
VOL
0.8 x VDD
â
â
â
VDD
V
0.4
Rise/Fall time (20/80%)
tR, tF
LVPECL/LVDS/CML
â
â
350
ps
CMOS with CL = 15 pF
â
2
â
ns
Symmetry (duty cycle)
SYM LVPECL: VDD â 1.3 V (diff)
LVDS: 1.25 V (diff)
45
â
55
%
CMOS: VDD/2
Notes:
1. 50 ï to VDD â 2.0 V.
2. Rterm = 100 ï (differential).
3. CL = 15 pF. Sinking or sourcing 12 mA for VDD = 3.3 V, 6 mA for VDD = 2.5 V, 3 mA for VDD = 1.8 V.
Table 4. CLK± Output Phase Jitter
Parameter
Symbol
Test Condition
Min Typ Max Units
Phase Jitter (RMS)1
for 50 MHz < FOUT < 810 MHz
(LVPECL/LVDS/CML)
Phase Jitter (RMS)1
(LVPECL/LVDS/CML)
ï¦J
12 kHz to 20 MHz
â 0.5 1.0 ps
ï¦J
12 kHz to 20 MHz,
â 0.4 0.7 ps
155.52 MHz output frequency
Phase Jitter (RMS)2
for 50 MHz < FOUT < 160 MHz
(CMOS)
ï¦J
12 kHz to 20 MHz
â 0.6 1.0 ps
Notes:
1. Refer to AN256 for further information.
2. Single-ended CMOS output phase jitter measured using 33 ï series termination into 50 ï phase noise test equipment.
3.3 V supply voltage option only.
Rev. 1.0
3
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