591BD-DDG Datasheet, PDF (1/12 Pages) List of Unclassifed Manufacturers – 1 ps MAX JITTER CRYSTAL OSCILLATOR (XO) (10 MHZ TO 810 MHZ)

Si590/591
1 ps MAX JITTER CRYSTAL OSCILLATOR (XO)
(10 MHZ TO 810 MHZ)
Features
 Available with any-frequency output  Available CMOS, LVPECL,
frequencies from 10 to 810 MHz
LVDS, and CML outputs
 3rd generation DSPLL^® with superior ^{ 3.3, 2.5, and 1.8 V supply options}
jitter performance: 1 ps max jitter ^{ Industry-standard 5 x 7 mm}
 Better frequency stability than SAW- ^{package and pinout}
based oscillators
 Pb-free/RoHS-compliant
 Internal fundamental mode crystal ^{ –40 to +85 ºC operating}
ensures high reliability
temperature range
Applications
 SONET/SDH (OC-3/12/48)
 Networking
 SD/HD SDI/3G SDI video
 Test and measurement
 Storage
 FPGA/ASIC clock generation
Description
The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL^® circuitry
to provide a low jitter clock at high frequencies. The Si590/591 supports any
frequency from 10 to 810 MHz. Unlike a traditional XO, where a unique
crystal is required for each output frequency, the Si590/591 uses one fixed
crystal to provide a wide range of output frequencies. This IC based
approach allows the crystal resonator to provide exceptional frequency
stability and reliability. In addition, DSPLL clock synthesis provides superior
supply noise rejection, simplifying the task of generating low jitter clocks in
noisy environments typically found in communication systems. The
Si590/591 IC based XO is factory configurable for a wide variety of user
specifications including frequency, supply voltage, output format, and
stability. Specific configurations are factory programmed at time of shipment,
thereby eliminating long lead times associated with custom oscillators.
Functional Block Diagram
V_DD
CLK– CLK+
Si5602
Ordering Information:
See page 7.
Pin Assignments:
See page 6.
(Top View)
NC 1
6 VDD
OE 2
5 CLK–
GND 3
4 CLK+
Si590 (LVDS/LVPECL/CML)
OE 1
NC 2
GND 3
6 VDD
5 NC
4 CLK
17 k *
Any-rate
Fixed
10–810 MHz
OE
Frequency
DSPLL^®
XO
Clock
Synthesis
17 k*
Si590 (CMOS)
OE 1
NC 2
GND 3
6 VDD
5 CLK–
4 CLK+
GND
*Note: Output Enable High/Low Options Available – See Ordering Information
Si591 (LVDS/LVPECL/CML)
Rev. 1.0 8/11
Copyright © 2011 by Silicon Laboratories
Si590/591