AK4620BVFP-E2 Datasheet, PDF (28/42 Pages) List of Unclassifed Manufacturers – 24-Bit 192kHz Audio CODEC with IPGA

ASAHI KASEI
[AK4620B]
„ Serial Control Interface
The internal registers may be written to the 3-wire µP interface pins: CSN, CCLK, CDTI. The data on this interface
consists of Chip address (2bits, C0/1) Read/Write (1 bit), Register address (MSB first, 5 bits) and Control data (MSB first,
8 bits). Address and data is clocked in on the rising edge of CCLK. Data is latched out after the 16th rising edge of CCLK,
following a high-to-low transition of CSN. Operation of the control serial port may be completely asynchronous with the
audio sample rate. The maximum clock speed of the CCLK is 5MHz. The chip address is fixed to “10”. The access to the
chip address except for “10” is invalid. PDN pin = “L” resets the registers to their default values.
Function
Parallel mode Serial mode
ADC Single-ended/Differential Input mode
X
X
Overflow detection
X
X
Zero detection
-
X
Soft Mute
-
X
Input Volume
-
X
Output Volume
-
X
HPF OFF
-
X
DSD mode
-
X
16/20/24 bit LSB justified format of DAC
-
X
MCLK = 256fs @ Quad Speed
-
X
De-emphasis: 32kHz, 48kHz
-
X
Table 17. Function List (X: available, -: not available)
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip A ddress (Fixed to “10”)
R/W: READ/WRITE (Fixed to “1”:WRITE)
A4-A0: Register Address
D7-D0: Cont rol data
Figure 13. Control I/F Timing
* READ command is not supported.
* The control data can not be written when the CCLK rising edge is 15times or less or 17times or more during CSN is “L”.
MS0401-E-00
- 28 -
2005/07