AK4620BVFP-E2 Datasheet, PDF (19/42 Pages) List of Unclassifed Manufacturers – 24-Bit 192kHz Audio CODEC with IPGA

ASAHI KASEI
[AK4620B]
MCLK (Normal speed)
256fs
512fs
1024fs
384fs
768fs
fs=44.1kHz
11.2896MHz
22.5792MHz
45.1584MHz
16.9344MHz
33.8688MHz
fs=48kHz
12.288MHz
24.576MHz
49.152MHz
18.432MHz
36.864MHz
MCLK (Double speed)
N/A
256fs
512fs
N/A
384fs
fs=88.2kHz
N/A
22.5792MHz
45.1584MHz
N/A
33.8688MHz
fs=96kHz
N/A
24.576MHz
49.152MHz
N/A
36.864MHz
MCLK (Quad speed)
128fs
256fs
192fs
fs=176.4kHz
22.5792MHz
45.1584MHz
33.8688MHz
fs=192kHz
24.576MHz
49.152MHz
36.864MHz
Table 8. Master clock frequency example
2. DSD Mode
The external clocks, which are required to operate the AK4620B, are MCLK and DCLK. The master clock (MCLK)
should be synchronized with DSD clock (DCLK) but the phase is not critical. The frequency of MCLK is set by DCKS
bit.
All external clocks (MCLK, DCLK) must be present whenever the AK4620B is in the normal operation mode (PDN pin
= “H”). If these clocks are not provided, the AK4620B may draw excess current because the device utilizes dynamically
refreshed logic. The AK4620B should be reset by PDN pin = “L” after these clocks are provided. If the external clocks are
not present, the AK4620B should be in the power-down mode (PDN pin = “L”). After exiting reset (PDN pin = “↑”) at
power-up etc., the AK4620B is in the power-down mode until MCLK is provided.
„ Audio Serial Interface Format
1. PCM Mode
Five serial modes are supported and selected by the DIF2-0 bits in Serial Mode (two modes by DIF pin in Parallel Mode)
as shown in Table 9 and Table 10. In all modes the serial data has MSB first, 2’s complement format. The SDTO is
clocked out on the falling edge of BICK and the SDTI is latched on the rising edge. Mode2 can be used for 20 and 16
MSB justified formats by zeroing the unused LSBs.
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
SDTO
SDTI
24bit, MSB justified 16bit, LSB justified
24bit, MSB justified 20bit, LSB justified
24bit, MSB justified 24bit, MSB justified
24bit, I²S
24bit, I²S
24bit, MSB justified 24bit, LSB justified
Table 9. Audio data format (Serial Mode)
LRCK
H/L
H/L
H/L
L/H
H/L
BICK
≥ 48fs
≥ 48fs
≥ 48fs
≥ 48fs
≥ 48fs
Default
Mode
2
3
DIF pin
L
H
SDTO
SDTI
LRCK
24bit, MSB justified 24bit, MSB justified H/L
24bit, I²S
24bit, I²S
L/H
Table 10. Audio data format (Parallel Mode)
BICK
≥ 48fs
≥ 48fs
MS0401-E-00
- 19 -
2005/07