KAD5512HP Datasheet, PDF (24/31 Pages) List of Unclassifed Manufacturers – High Performance 12-Bit, 250/210/170/125MSPS ADC

KAD5512HP
operation, nap or sleep modes (refer to Nap/Sleep
section). This functionality can be overridden and
controlled through the SPI. This is an indexed function
when controlled from the SPI, but a global function
when driven from the pin. This register is not changed
by a Soft Reset.
Value
0x25[2:0]
Power Down Mode
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
Table 10. Power Down Control
Global DUT Configuration/Control
Figure 45. Phase Slip
Address 0x72: clock_divide
The KAD5512HP has a selectable clock divider that
can be set to divide by four, two or one (no division).
By default, the tri-level CLKDIV pin selects the divisor
(refer to Clock Input section). This functionality can be
overridden and controlled through the SPI, as shown
in Table 12. This register is not changed by a Soft Reset.
Address 0x70: skew_diff
The value in the skew_diff register adjusts the timing
skew between the two ADCs cores. The nominal
range and resolution of this adjustment are given in
Table 11. The default value of this register after power-
up is 00h.
Value
000
001
010
0x72[2:0]
Clock Divider
Pin Control
Divide by 1
Divide by 2
Parameter
Steps
0x70[7:0]
Differential Skew
256
100
Divide by 4
Table 12. Clock Divider Selection
Address 0x73: output_mode_A
–Full Scale (0x08)
-6.5ps
The output_mode_A register controls the physical out-
Mid–Scale (0x00)
0.0ps
put format of the data, as well as the logical coding.
The KAD5512HP can present output data in two physi-
+Full Scale (0x07)
+6.5ps
cal formats: LVDS or LVCMOS. Additionally, the drive
Nominal Step Size
51fs
strength in LVDS mode can be set high (3mA) or low
(2mA). By default, the tri-level OUTMODE pin selects
Table 11. Differential Skew Adjustment
the mode and drive level (refer to Digital Outputs sec-
Address 0x71: phase_slip
tion). This functionality can be overridden and con-
trolled through the SPI, as shown in Table 13.
When using a clock divider, it’s not possible to deter-
mine the synchronization of the incoming and divided
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default,
clock phases. This is particularly important when multi-
ple ADCs are used in a time-interleaved system. The
phase slip feature allows the rising edge of the divided
clock to be advanced by one input clock cycle, as
shown in Figure 45.
the tri-level OUTFMT pin selects the data format (refer
to Data Format section). This functionality can be over-
ridden and controlled through the SPI, as shown in Ta-
ble 14.
This register is not changed by a Soft Reset.
Rev 0.5 Preliminary
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