KAD5512HP Datasheet, PDF (21/31 Pages) List of Unclassifed Manufacturers – High Performance 12-Bit, 250/210/170/125MSPS ADC

KAD5512HP
3.79MHz for write operations. There is no minimum
SCLK rate.
The following sections describe various registers that
are used to configure the SPI or adjust performance
or functional parameters. Many registers in the avail-
able address space (0x00 to 0xFF) are not defined in
this document. Additionally, within a defined register
there may be certain bits or bit combinations that
are reserved. Undefined registers and undefined val-
ues within defined registers are reserved and should
not be selected. Setting any reserved register or
value may produce indeterminate results.
SPI Physical Interface
The SPI port operates in a half or full duplex mas-
ter/slave configuration, with the KAD5512HP function-
ing as a slave. Multiple slave devices can interface to
a single master. The chip-select bar (CSB) pin deter-
mines when a slave device is being addressed. Multi-
ple slave devices can be written to concurrently, but
only one slave device can be read from at a given
time. If multiple slave devices are selected for read-
ing at the same time, the results will be indetermi-
nate.
The serial clock pin (SCLK) provides synchronization
for the data transfer. By default, all data is presented
on the serial data input/output (SDIO) pin. The state
of the SDIO pin is set automatically in the communi-
cation protocol (described below). A dedicated se-
rial data output pin (SDO) can be activated by set-
ting 0x00[7] high to allow operation in full duplex
mode.
The communication protocol begins with an instruc-
tion/address phase. The first rising SCLK edge follow-
ing a high to low transition on CSB determines the
beginning of the two-byte instruction/address com-
mand. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be
changed by setting 0x00[6] high. Figures 40 and 41
show the appropriate bit ordering for the MSB-first
and LSB-first modes, respectively. In MSB-first mode
the address is incremented for multi-byte transfers,
while in LSB-first mode it’s decremented.
In the default mode the MSB is R/W, which deter-
mines if the data is to be read (active high) or writ-
ten. The next two bits, W1 and W0, determine the
number of data bytes to be read or written (see Ta-
ble 6). The lower 13 bits contain the first address for
the data transfer. This relationship is illustrated in Fig-
ure 42, and timing values are given in the Switching
Specifications section.
After the instruction/address bytes have been read,
the appropriate number of data bytes are written to
or read from the ADC (based on the R/W bit status).
The data transfer will continue as long as CSB remains
low and SCLK is active. Stalling of the CSB pin is al-
lowed at any byte boundary (instruction/address or
data) if the number of bytes being transferred is three
or less. For transfers of four bytes or more, CSB is al-
lowed stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to
a high state after that point the state machine will
reset and terminate the data transfer.
Figure 40. MSB-First Addressing
Rev 0.5 Preliminary
Figure 41. LSB-First Addressing
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