ZADCS1082_11 Datasheet, PDF (20/27 Pages) List of Unclassifed Manufacturers – 10-Bit, 250ksps, ADC Family

ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
nCS
SCLK
1
8
1
8
1
8
DIN
SSTRB
S A2 A1
(Start)
Idle
A0 UNI/ SGL/ PD1 PD0
BIP DIF
Acquire
Conversion
S A2 A1 A0 UNI/ SGL/ PD1 PD0
BIP DIF
Idle
Acquire
DOUT
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
(MSB)
(LSB)
Figure 13: 16-Clock External Clock Mode Conversion
Zero filled
1
B9 B8
nCS
SCLK
1
8
13 1
13 1
DIN
SSTRB
S A2 A1
(Start)
Idle
A0 UNI/ SGL/ PD1 PD0
BIP DIF
Acquire
S A2 A1 A0 UNI/ SGL/ PD1 PD0
BIP DIF
Conversion
Acquire
S A2 A1 A0
Conversion
DOUT
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
(MSB)
(LSB)
Figure 14: 13-Clock External Clock Mode Conversion
Zero filled
B9 B8 B7 B6 B5 B4 B3 B2
Internal Clock Mode
In Internal Clock Mode, the conversion starts at the falling clock edge of the eighth control bit just as in
External Clock Mode. However, there are no further clock pulses required at SCLK to complete the
conversion. The conversion clock is generated by an internal oscillator that runs at approximately 3.3MHz.
While the conversion is running, the SSTRB signal is driven LOW. As soon as the conversion is complete,
SSTRB is switched to HIGH, signalling that the conversion result can be read out on the serial interface. To
shorten cycle times ZADCS10x2 family devices allow interleaving of the read out process with the
transmission of a new control byte. Thus it is possible to read the conversion result and to start a new
conversion with just two consecutive byte transfers, instead of thee bytes that would have to be send without
the interleaving function. While the IC is performing a conversion in Internal Clock Mode, the Chip Select
signal (nCS) may be tied HIGH allowing other devices to communicate on the bus. The output driver at DOUT
is switched into a high impedance state while nCS is HIGH. The conversion time t_CONV may vary in the
specified limits depending on the actual VDD and temperature values.
16-Clocks per Conversion
Interleaving of the data read out process and transmission of a new Control Byte is also supported for
External Clock Mode operation. Figure 13 shows the transmission timing for conversion runs using 16 clock
cycles per run.
13-Clocks per Conversion
ZADCS10x2 family devices do also support a 13 clock cycle conversion mode (see Figure 14). This is the
fastest conversion mode possible. In fact, the specified converter sampling rate of 250ksps will be reached in
this mode, provided the clock frequency is set to 3.3MHz. Usually micro controllers do not support this kind of
13 bit serial communication transfers. However, specifically designed digital state machines implemented in
Data Sheet
October 12, 2011
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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