ZADCS1082_11 Datasheet, PDF (19/27 Pages) List of Unclassifed Manufacturers – 10-Bit, 250ksps, ADC Family

ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
nCS
SCLK
1
t _ACQ
8
1
8
1
DIN
SSTRB
S A2 A1
(Start)
Idle
A0 UNI/ SGL/ PD1 PD0
BIP DIF
Acquire
Conversion
DOUT
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
(MSB)
(LSB)
Figure 11: 24-Clock External Clock Mode Timing (f_SCLK ≤ 3.3MHz)
8
Idle
Zero filled
nCS
SCLK
1
8
1
8
1
8
DIN
S A2 A1 A0 UNI/ SGL/ PD1 PD0
BIP DIF
(Start)
Idle
Acquire
Conversion
S A2 A1 A0 UNI/ SGL/ PD1 PD0
BIP DIF
Result Output
Acquire
SSTRB
DOUT
t _CONV
B9 B8 B7 B6 B5 B4 B3 B2
(MSB)
Figure 12: Internal Clock Mode Timing with interleaved Control Byte transmission
B1 B0
(LSB)
Zero filled
BIT
Name Description
7
(MSB)
START
The Start Bit is defined by the first logic ‘1’ after nCS goes low.
6
A2
Channel Select Bits. Along with SGL/DIF these bits control the setting of the input multiplexer.
5
A1
For further details on the decoding see also Table 5 and Table 6.
4
A0
3
UNI/BIP Output Code Bit. The value of the bit determines conversion mode and output code format.
‘1’
=
unipolar - straight binary coding
‘0’
=
bipolar - two’s complement coding
2
SGL/DIF Single-Ended / Differential Select Bit. Along with the Channel Select Bits A2 .. A0 this bit
controls the setting of the input multiplexer
‘1’
=
single ended - all channels CH0 … CH7 measured referenced to COM
‘0’
=
differential - the voltage between two channels is measured
1
PD1
0 (LSB) PD0
Power Down and Clock Mode Select Bits
PD1 PD0 Mode
0
0
Full Power-Down
0
1
Fast Power-Down
1
0
Internal clock mode
1
1
External clock mode
Table 7 Control Byte Format
Data Sheet
October 12, 2011
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
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