TC5747 Datasheet, PDF (18/44 Pages) List of Unclassifed Manufacturers – Single Chip CMOS Imager with Integrated Image Signal Processor and JPEG Codec

TC5747 Data Sheet
Single Chip CMOS Imager
Each of the two output units, the PVI and SVI have a serial clock whose frequency is a multiple of the input
clock. Each clock, rclkp and rclks is configured separately.
3.3 Device Initialization Sequence
PS1/2 PowerDown =01 Startup =00
Full On =10
RESET_N
Bypass (Default)
Active PLL
Set PLL ^{Enter PLL}
mode ^mode
CLKIN
BYPASS
PLL_PD
RCLK
PLL lock time
PLL_mode = required working multiply
Figure 3: Initialization Sequence
The Initialization sequence includes the following steps:
1 After system power-up, the Power Save pins should be put into Startup mode.
2 Clock input and RESET_N should be activated.
3 After the Regulators’ wake up time, the Power Save pins should be put into Full-on mode.
4 RESET_N is deactivated.
5 PLL mode should be set.
6 After PLL lock time, Bypass mode may be deactivated.
When working in Bypass mode, steps 5 and 6 may be skipped.
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