RFM75 Datasheet, PDF (16/27 Pages) List of Unclassifed Manufacturers – Low Power High Performance 2.4 GHz GFSK Transceiver

RFM75 V1.0
03
SETUP_AW
Reserved
7:2
AW
1:0
04
SETUP_RETR
ARD
7:4
ARC
3:0
05
RF_CH
Reserved
7
RF_CH
6:0
06
RF_SETUP
Reserved
7:6
RF_DR_LOW
5
PLL_LOCK
4
RF_DR_HIGH
3
RF_PWR[1:0]
2:1
LNA_HCURR
0
07
STATUS
RBANK
7
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000000 R/W
11
R/W
0000
R/W
0011
R/W
0
R/W
0000010 R/W
0
R/W
0
R/W
0
R/W
1
R/W
11
R/W
1
R/W
0
R
Setup of Address Widths
(common for all data pipes)
Only '000000' allowed
RX/TX Address field width
'00' - Illegal
'01' - 3 bytes
'10' - 4 bytes
'11' - 5 bytes
LSB bytes are used if address width is
below 5 bytes
Setup of Automatic Retransmission
Auto Retransmission Delay
‘0000’ – Wait 250 us
‘0001’ – Wait 500 us
‘0010’ – Wait 750 us
……..
‘1111’ – Wait 4000 us
(Delay defined from end of transmission to
start of next transmission)
Auto Retransmission Count
‘0000’ –Re-Transmit disabled
‘0001’ – Up to 1 Re-Transmission on fail
of AA
……
‘1111’ – Up to 15 Re-Transmission on fail
of AA
RF Channel
Only '0' allowed
Sets the frequency channel
RF Setup Register
Only '00' allowed
Set Air Data Rate. See RF_DR_HIGH for
encoding.
Force PLL lock signal. Only used in test
Set Air Data Rate.
Encoding: RF_DR_LOW, RF_DR_HIGH:
‘00’ – 1Mbps
‘01’ – 2Mbps (default)
‘10’ – 250Kbps
‘11’ – 2Mbps
Set RF output power in TX mode
RF_PWR[1:0]
Setup LNA gain
0:Low gain(20dB down)
1:High gain
Status Register (In parallel to the SPI
command word applied on the MOSI pin,
the STATUS register is shifted serially out
on the MISO pin)
Register bank selection states. Switch
register bank is done by SPI command
“ACTIVATE” followed by 0x53
0: Register bank 0
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