ARM7TDMI_G Datasheet, PDF (157/284 Pages) List of Unclassifed Manufacturers – Technical Reference Manual

Instruction Cycle Timings
6.9 Load multiple registers
The first cycle of the LDM instruction is used to calculate the address of the first word
to be transferred, while performing a prefetch from memory. The second cycle fetches
the first word, and performs the base modification. During the third cycle, the first word
is moved to the appropriate destination register while the second word is fetched from
memory, and the modified base is latched internally in case it is needed to restore
processor state after an abort. The third cycle is repeated for subsequent fetches until the
last data word has been accessed, then the final (internal) cycle moves the last word to
its destination register. The cycle timings are listed in Table 6-12.
The last cycle can be merged with the next instruction prefetch to form a single memory
N-cycle. If an abort occurs, the instruction continues to completion, but all register
modification after the abort is prevented. The final cycle is altered to restore the
modified base register (that could have been overwritten by the load activity before the
abort occurred).
When the PC is in the list of registers to be loaded the current instruction pipeline must
be invalidated.
Note
The PC is always the last register to be loaded, so an abort at any point prevents the PC
from being overwritten.
LDM with PC as a destination register is not available in Thumb state. Use
POP{Rlist,PC} to perform the same function.
Destination registers
Single register
Table 6-12 Load multiple registers instruction cycle operations
Cycle Address MAS[1:0] nRW Data nMREQ SEQ nOPC
1
pc+2L
i
2
alu
2
3
pc+3L
i
pc+3L
0
(pc+2L) 0
0
(alu)
1
0
-
0
0
0
0
1
1
1
ARM DDI 0029G
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