ARM7TDMI_G Datasheet, PDF (110/284 Pages) List of Unclassifed Manufacturers – Technical Reference Manual

Coprocessor Interface
4.4 Coprocessor interface handshaking
Coprocessor interface handshaking is described as follows:
• The coprocessor on page 4-6
• The ARM7TDMI processor on page 4-7
• Coprocessor signaling on page 4-7
• Consequences of busy-waiting on page 4-8
• Coprocessor register transfer instructions on page 4-9
• Coprocessor data operations on page 4-10
• Coprocessor load and store operations on page 4-10.
The ARM7TDMI core and any coprocessors in the system perform a handshake using
the signals shown in Table 4-2.
Table 4-2 Handshaking signals
Signal Direction
Meaning
nCPI
CPA
CPB
ARM7TDMI core to coprocessor NOT coprocessor instruction
Coprocessor to ARM7TDMI core Coprocessor absent
Coprocessor to ARM7TDMI core Coprocessor busy
These signals are explained in more detail in Coprocessor signaling on page 4-7.
4.4.1
The coprocessor
The coprocessor decodes the instruction currently in the Decode stage of its pipeline,
and checks whether that instruction is a coprocessor instruction. A coprocessor
instruction contains a coprocessor number that matches the coprocessor ID of the
coprocessor.
If the instruction currently in the Decode stage is a relevant coprocessor instruction:
1. The coprocessor attempts to execute the instruction.
2. The coprocessor handshakes with the ARM7TDMI core using CPA and CPB.
Note
The coprocessor can drive CPA and CPB as soon as it decodes the instruction. It does
not have to wait for nCPI to be LOW but it must not commit to execute the instruction
until nCPI has gone LOW.
4-6
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