ARM7TDMI_G Datasheet, PDF (103/284 Pages) List of Unclassifed Manufacturers – Technical Reference Manual

Memory Interface
3.10 Reset sequence after power up
It is good practice to reset a static device immediately on power-up, to remove any
undefined conditions within the device that can otherwise combine to cause a DC path
and consequently increase current consumption. Most systems are reset by using a
simple RC circuit on the reset pin to remove the undefined states within devices whilst
clocking the device.
During reset, the signals nMREQ and SEQ show internal cycles where the address bus
continues to increment by two or four bytes. The initial address and increment values
are determined by the state of the core when nRESET was asserted. They are undefined
after power up.
After nRESET has been taken HIGH, the ARM core does two further internal cycles
before the first instruction is fetched from the reset vector (address 0x00000000). It then
takes three MCLK cycles to advance this instruction through the
Fetch-Decode-Execute stages of the ARM instruction pipeline before this first
instruction is executed. This is shown in Figure 3-22.
Note
nRESET must be held asserted for a minimum of two MCLK cycles to fully reset the
core.
You must reset the EmbeddedICE Logic and the TAP controller as well, whether the
debug features are used or are not. This is done by taking nTRST LOW for at least T_bsr,
no later than nRESET.
In Figure 3-22, x, y, and z are incrementing address values.
ARM DDI 0029G
MCLK
nRESET
A[31:0]
D[31:0]
nMREQ
SEQ
nEXEC
Fetch 1 Decode 1 Execute 1
x
y
z
0
4
8
Figure 3-22 Reset sequence
Copyright © 1994-2001. All rights reserved.
3-33