PS20230 Datasheet, PDF (15/26 Pages) List of Unclassifed Manufacturers – COFDM demodulator with USB interface for PC-TV

PS20230
Figure 7 FEC block diagram
The FSM controller shown in Figure 6controls both the demodulator and the FEC. The controller
facilitates the automated search of all parameters or any sub-set of parameters of the received signal.
This mechanism provides the fast channel scan and acquisition performance, whilst requiring minimal
software overhead in the driver.
The algorithms and architectures used in the PS20230 have been optimized to minimize power
consumption.
7.1 Analogue-to-Digital Converter
The PS20230 has a high performance 10-bit analogue-to-digital converter (ADC) which can sample a 6,
7 or 8 MHz bandwidth OFDM signal, with its spectrum centered at:
• 36.17 MHz IF
• 43.75 MHz IF
• 5 - 10 MHz near-zero IF
An on-chip programmable phase locked loop (PLL) is used to generate the ADC sampling clock. The
PLL is highly programmable allowing a wide choice of sampling frequencies to suit any IF frequency, and
all signal bandwidths.
The PS20230 features a 7-bit RF signal level monitor ADC in addition to the main 10-bit ADC.
7.2 Automatic Gain Control
An AGC module compares the absolute value of the digitized signal with a programmable reference. The
error signal is filtered and is used to control the gain of the amplifier. A sigma-delta modulated output is
provided, which has to be RC low-pass filtered to obtain the voltage to control the amplifier.
The bandwidth of the AGC is set to a large value for quick acquisition then reduced to a small value for
tracking.
The AGC is free running during OFDM channel changes and locks to the new channel while the tuner
lock is being established. This is one of the features of PS20230 used to minimize acquisition time. A
robust AGC lock mechanism is provided and the other parts of the PS20230 begin to acquire only after
the AGC has locked.
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